addr_fsm.v

design compile synthesis user guide

//*************************************************************
//  FSM block for RTL Analyzer tutorial
//*************************************************************
//
// Revision 1.1  1998/06/08  dannyb
// modify to match VHDL
//*************************************************************

`timescale 1ns/10ps

module addr_fsm ( RST, CLK , AS, BREQ, ADDR, CS, ENABLE_SELECT, BUS_ENABLE );
   input RST ;
   input CLK ;
   input AS ;
   input BREQ ;
   input [15:0] ADDR ;
   output [2:0] CS ;
   output [2:0] ENABLE_SELECT ;
   output BUS_ENABLE ;

   wire [2:0] CS ;
   reg [2:0] ENABLE_SELECT ;
   wire BUS_ENABLE ;
   
   parameter[3:0] // synopsys enum STATE
   s0 = 4'd0, s1 = 4'd1, 
   s2 = 4'd2, s3 = 4'd3, 
   s4 = 4'd4, s5 = 4'd5,
   s6 = 4'd6, s7 = 4'd7, 
   s8 = 4'd8, s9 = 4'd9;
   reg [3:0] /* synopsys enum STATE */ CURRSTATE, NEXTSTATE ;

   wire [2:0] INTCSO ;
   reg [2:0] INTEN, INTCS;
   reg BUSACK ;

   assign INTCSO = INTEN | {AS, AS, AS};
   assign BUS_ENABLE = BUSACK | (&INTCSO);
   assign CS = INTCS | {AS, AS, AS};

  always @ (ADDR)
  begin

    if (ADDR[15] == 1'b1) 
      INTEN = 3'b011;
    else if (ADDR[11] == 1'b1) 
      INTEN = 3'b101;
    else if (ADDR[7] == 1'b1) 
      INTEN = 3'b110;
    else INTEN = 3'b111;
  end //always @ ADDR

  always @ (negedge RST or posedge CLK )
  begin: flops
    if (RST == 1'b0)
      CURRSTATE = s0;
    else 
     CURRSTATE = NEXTSTATE;
  end //always @ -ve RST or +ve CLK

  always @ (CURRSTATE or AS or INTCSO or BREQ)
  begin: fsm
    ENABLE_SELECT = 3'b000;
    INTCS = 3'b111;
    BUSACK = 1'b1;
    NEXTSTATE = CURRSTATE;

    case (CURRSTATE) //synopsys full_case parallel_case
      s0: state_0;
      s1: state_1;
      s2: state_2;
      s3: state_3;
      s4: state_4;
      s5: state_5;
      s6: state_6;
      s7: state_7;
      s8: state_8; 
      s9: state_9;
      default: state_default;
    endcase //CURSTATE
  end

  task state_default;
  begin
    NEXTSTATE = s0;
  end
  endtask //state_default
  
  task state_0;
  begin
    INTCS = 3'b111;
    BUSACK = 1'b1;
    if (BREQ == 1'b1) begin
      ENABLE_SELECT = 3'b001;
      NEXTSTATE = s3;
    end
    else if (INTCSO[2] == 1'b0) begin
      ENABLE_SELECT = 3'b010;
      NEXTSTATE = s1;
    end
    else if (INTCSO[1] == 1'b0) begin
      ENABLE_SELECT = 3'b100;
      NEXTSTATE = s2;
    end
    else if (INTCSO[0] == 1'b0) begin
      ENABLE_SELECT = 3'b111;
      NEXTSTATE = s4;
    end
    else begin
      ENABLE_SELECT = 3'b000;
      NEXTSTATE = s0;
    end
  end
  endtask //state_0
    
  
  task state_1;
  begin
    INTCS[2] = 1'b0;
    NEXTSTATE = s5;
  end
  endtask //state_1
  
  task state_5;
  begin
    INTCS[2] = 1'b0;
    NEXTSTATE = s6;
  end
  endtask //state_5
  
  task state_7;
  begin
    INTCS[2] = 1'b0;
    if (AS == 1'b1)
      NEXTSTATE = s0;
  end
  endtask //state_7
  
  task state_6;
  begin
    INTCS[2] = 1'b0;
    NEXTSTATE = s7;
  end
  endtask //state_6
  
  task state_2;
  begin
    NEXTSTATE = s9;
  end
  endtask //state_9
  
  task state_9;
  begin
    INTCS[1] = 1'b0;
    if (AS == 1'b1)
      NEXTSTATE = s0;
  end
  endtask //state_9
  
  task state_3;
  begin
    BUSACK = 1'b1;
    if (BREQ == 1'b0)
      NEXTSTATE = s8;
  end
  endtask //state_3
  
  task state_8;
  begin
    BUSACK = 1'b0;
    NEXTSTATE = s0;
  end
  endtask //state_8
  
  task state_4;
  begin
    INTCS[0] = 1'b0;
    if (AS == 1'b1)
      NEXTSTATE = s0;
  end
  endtask //state_4

endmodule // addr_fsm