gtech_fast.scr

design compile synthesis user guide

/*************************************************************/
/*  Script to create the GTECH view of the design  which is  */
/*  compatible with RTL Analyzer                             */
/*                                                           */
/*  1 command has been added to the original dc_shell script */
/*  to support the use of RTL Analyzer                       */
/*************************************************************/

echo "Running Source to GTECH phase of design";

/* creating a variable to be used for analyzing */
/* the design and writing out reports           */
toplevel = "top";

/* Define variable for source files */
verilog_files = { addr_combo_fast.v \
                  addr_fsm.v \
                  top.v \
                };

/* analyze all of the blocks in this design  */
analyze -f verilog verilog_files;

/* elaborate the circuit (hierarchical elaborate) */
elaborate toplevel;

link;

current_design = toplevel;

/* include the script to apply constraints to the design */
include constraints.scr;

check_design > report_dir + toplevel + "_fast_gtech_chk.rpt";

                /* RTL Analyzer specific */
/* Write out GTECH database and RTL Analyzer Project file, */ 
/* start RTL Analyzer GUI and load GTECH design            */
rtl_analyzer -output unmapped_dir + toplevel + "_fast_gtech.db" \
             -project proj_dir + toplevel + "_fast_gtech.proj";