recompile.scr

design compile synthesis user guide

/*************************************************************/
/*  Script to recompile the design with high effort compile  */
/*  options set.                                             */
/*                                                           */
/*************************************************************/

/* Set required variables */
include scripts/setup_fast.scr;

/* Read the fast mapped design previously created */
read top_fast_mapped.db;

/* creating a variable to be used for writing out reports */
toplevel = "top";

/* High effort recompile  */
compile -incremental_mapping -map_effort high;

              /* RTL Analyzer specific */
/* Write out Mapped database and RTL Analyzer Project file, */
/* -dont_start option used to supress sarting the GUI       */
rtl_analyzer -output mapped_dir + toplevel + "_recomp_fast_mapped.db" \
             -project proj_dir + toplevel + "_recomp_fast_mapped.proj";
  
report_timing > report_dir + toplevel + "_recomp_fast_timing.rpt";
    
report_area > report_dir + toplevel + "_recomp_fast_area.rpt";

exit;