setup.scr

design compile synthesis user guide

/*************************************************************/
/*  Script to set up the required veriables for running the  */
/*  RTL Analyzer Tutorial                                    */
/*                                                           */
/*  2 variables have been added to the original dc_shell     */
/*  script to support the use of RTL Analyzer                */
/*************************************************************/

                /* RTL Analyzer specific */
/* Enable the generation of tracing information              */
hdlin_enable_analysis_info = "true";

                /* RTL Analyzer specific */
/* Direct all of the *.bi, *.id, *.ra files generated to the */
/* ./gtech directory                                         */
hdlin_write_gtech_design_directory = "./gtech";

/* Define variables for subdirectories used */
work_lib_path = "./work_lib";
src_dir = "./hdl/";
mapped_dir = "./mapped/";
unmapped_dir = "./unmapped/";
report_dir = "./reports/";
script_dir = "./scripts/";
lib_dir = "./libs/";
proj_dir = "./projs/";

/* Define WORK directory to store files created by dc_shell */
define_design_lib WORK -path work_lib_path;

/* Add subdirectories to search path */
search_path = search_path + { work_lib \
  src_dir \
  mapped_dir \
  unmapped_dir \
  report_dir \
  script_dir \
  lib_dir \
  proj_dir \
  };