top_mapped.proj

design compile synthesis user guide

set link_library " \
                     class.db \
                     standard.sldb \
                     dw01.sldb \
                     dw02.sldb \
                   "
set target_library " \
                     class.db \
                   "
set apply_constraints_on_gtech true
set dont_load_mapped_design " false "
set search_path " \
                     . \
                     ./mapped \
                     $env(SYNOPSYS)/libraries/syn \
                     $env(SYNOPSYS)/dw/sim_ver \
                     work_lib \
                     ./hdl/ \
                     ./mapped/ \
                     ./unmapped/ \
                     ./reports/ \
                     ./scripts/ \
                     ./libs/ \
                     ./projs/ \
                     ./work_lib \
                     $env(SYNOPSYS)/dw/dw01/lib \
                     $env(SYNOPSYS)/dw/dw02/lib \
                     $env(SYNOPSYS)/dw/dw03/lib \
                     $env(SYNOPSYS)/dw/dw04/lib \
                     $env(SYNOPSYS)/dw/dw06/lib \
                     $env(SYNOPSYS)/dw/dw07/lib \
                     $env(SYNOPSYS)/dw/dw08/lib \
                     $env(SYNOPSYS)/packages/dware/lib \
                     $env(SYNOPSYS)/packages/gscomp/lib \
                     $env(SYNOPSYS)/packages/gtech/lib \
                     $env(SYNOPSYS)/packages/IEEE/lib \
                     $env(SYNOPSYS)/packages/IEEE_asic/lib \
                     $env(SYNOPSYS)/packages/synopsys/lib \
                     $env(SYNOPSYS)/packages/VITAL/lib \
                     ./work_lib \
                   "
set top_design_name " top "
set mapped_top_db_file " ./mapped/top_mapped.db "
set gtech_top_db_file " ./gtech/top.ra "
set gtech_db_files " \
                     ./gtech/top.ra \
                     ./gtech/addr_combo.ra \
                     ./gtech/addr_fsm.ra \
                   "