top_cons.scr

design compile synthesis user guide

/******************************************************

 Created by write_script() on Thu Jul 13 16:32:55 2000

******************************************************/

/* Set the current_design */
current_design addr_fsm

set_local_link_library {class.db}
remove_wire_load_model

/* Set the current_design */
current_design addr_combo_DW01_sub_8_2

set_max_delay 0\
	-to      find(port,"DIFF[7]")
set_max_delay 0\
	-to      find(port,"DIFF[6]")
set_max_delay 0\
	-to      find(port,"DIFF[5]")
set_max_delay 0\
	-to      find(port,"DIFF[4]")
set_max_delay 0\
	-to      find(port,"DIFF[3]")
set_max_delay 0\
	-to      find(port,"DIFF[2]")
set_max_delay 0\
	-to      find(port,"DIFF[1]")
set_max_delay 0\
	-to      find(port,"DIFF[0]")
set_max_delay 0\
	-to      find(port,"CO")
set_local_link_library {class.db}
remove_wire_load_model

/* Set the current_design */
current_design addr_combo_DW01_add_11_2

set_max_delay 0\
	-to      find(port,"SUM[10]")
set_max_delay 0\
	-to      find(port,"SUM[9]")
set_max_delay 0\
	-to      find(port,"SUM[8]")
set_max_delay 0\
	-to      find(port,"SUM[7]")
set_max_delay 0\
	-to      find(port,"SUM[6]")
set_max_delay 0\
	-to      find(port,"SUM[5]")
set_max_delay 0\
	-to      find(port,"SUM[4]")
set_max_delay 0\
	-to      find(port,"SUM[3]")
set_max_delay 0\
	-to      find(port,"SUM[2]")
set_max_delay 0\
	-to      find(port,"SUM[1]")
set_max_delay 0\
	-to      find(port,"SUM[0]")
set_max_delay 0\
	-to      find(port,"CO")
set_local_link_library {class.db}
remove_wire_load_model

/* Set the current_design */
current_design addr_combo_DW01_add_20_0

set_local_link_library {class.db}
set_max_area 0
remove_wire_load_model

/* Set the current_design */
current_design addr_combo_DW01_sub_11_0

set_local_link_library {class.db}
set_max_area 0
remove_wire_load_model

/* Set the current_design */
current_design addr_combo_DW01_cmp2_16_0

set_flatten false
set_structure true
set_local_link_library {class.db}
remove_wire_load_model

/* Set the current_design */
current_design addr_combo

set_local_link_library {class.db}
remove_wire_load_model

/* Set the current_design */
current_design top

create_clock -name "vclock" -period 10 -waveform {0 5} find(port,"CLK")
set_input_delay 0.1 -clock "vclock" find(port,"DOUT_SELECT")
set_input_delay 0.1 -clock "vclock" find(port,"WR_PT_L")
set_input_delay 0.1 -clock "vclock" find(port,"SELECT_PT_L")
set_input_delay 0.1 -clock "vclock" find(port,"ADR_PT[0]")
set_input_delay 0.1 -clock "vclock" find(port,"ADR_PT[1]")
set_input_delay 0.1 -clock "vclock" find(port,"ADR_PT[2]")
set_input_delay 0.1 -clock "vclock" find(port,"BREQ")
set_input_delay 0.1 -clock "vclock" find(port,"AS")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_POINTER[0]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_POINTER[1]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_POINTER[2]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_POINTER[3]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_POINTER[4]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_POINTER[5]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_POINTER[6]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_POINTER[7]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_POINTER[0]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_POINTER[1]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_POINTER[2]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_POINTER[3]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_POINTER[4]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_POINTER[5]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_POINTER[6]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_POINTER[7]")
set_input_delay 0.1 -clock "vclock" find(port,"ADDR[0]")
set_input_delay 0.1 -clock "vclock" find(port,"ADDR[1]")
set_input_delay 0.1 -clock "vclock" find(port,"ADDR[2]")
set_input_delay 0.1 -clock "vclock" find(port,"ADDR[3]")
set_input_delay 0.1 -clock "vclock" find(port,"ADDR[4]")
set_input_delay 0.1 -clock "vclock" find(port,"ADDR[5]")
set_input_delay 0.1 -clock "vclock" find(port,"ADDR[6]")
set_input_delay 0.1 -clock "vclock" find(port,"ADDR[7]")
set_input_delay 0.1 -clock "vclock" find(port,"ADDR[8]")
set_input_delay 0.1 -clock "vclock" find(port,"ADDR[9]")
set_input_delay 0.1 -clock "vclock" find(port,"ADDR[10]")
set_input_delay 0.1 -clock "vclock" find(port,"ADDR[11]")
set_input_delay 0.1 -clock "vclock" find(port,"ADDR[12]")
set_input_delay 0.1 -clock "vclock" find(port,"ADDR[13]")
set_input_delay 0.1 -clock "vclock" find(port,"ADDR[14]")
set_input_delay 0.1 -clock "vclock" find(port,"ADDR[15]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_OFFSET[0]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_OFFSET[1]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_OFFSET[2]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_OFFSET[3]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_OFFSET[4]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_OFFSET[5]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_OFFSET[6]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_OFFSET[7]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_OFFSET[8]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_OFFSET[9]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_OFFSET[10]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_OFFSET[11]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_OFFSET[12]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_OFFSET[13]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_OFFSET[14]")
set_input_delay 0.1 -clock "vclock" find(port,"WRITE_OFFSET[15]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_OFFSET[0]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_OFFSET[1]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_OFFSET[2]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_OFFSET[3]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_OFFSET[4]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_OFFSET[5]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_OFFSET[6]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_OFFSET[7]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_OFFSET[8]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_OFFSET[9]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_OFFSET[10]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_OFFSET[11]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_OFFSET[12]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_OFFSET[13]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_OFFSET[14]")
set_input_delay 0.1 -clock "vclock" find(port,"READ_OFFSET[15]")
set_input_delay 0.1 -clock "vclock" find(port,"INST_OFFSET[0]")
set_input_delay 0.1 -clock "vclock" find(port,"INST_OFFSET[1]")
set_input_delay 0.1 -clock "vclock" find(port,"INST_OFFSET[2]")
set_input_delay 0.1 -clock "vclock" find(port,"INST_OFFSET[3]")
set_input_delay 0.1 -clock "vclock" find(port,"INST_OFFSET[4]")
set_input_delay 0.1 -clock "vclock" find(port,"INST_OFFSET[5]")
set_input_delay 0.1 -clock "vclock" find(port,"INST_OFFSET[6]")
set_input_delay 0.1 -clock "vclock" find(port,"INST_OFFSET[7]")
set_input_delay 0.1 -clock "vclock" find(port,"INST_OFFSET[8]")
set_input_delay 0.1 -clock "vclock" find(port,"INST_OFFSET[9]")
set_input_delay 0.1 -clock "vclock" find(port,"INST_OFFSET[10]")
set_input_delay 0.1 -clock "vclock" find(port,"INST_OFFSET[11]")
set_input_delay 0.1 -clock "vclock" find(port,"INST_OFFSET[12]")
set_input_delay 0.1 -clock "vclock" find(port,"INST_OFFSET[13]")
set_input_delay 0.1 -clock "vclock" find(port,"INST_OFFSET[14]")
set_input_delay 0.1 -clock "vclock" find(port,"INST_OFFSET[15]")
set_input_delay 0.1 -clock "vclock" find(port,"BASE[0]")
set_input_delay 0.1 -clock "vclock" find(port,"BASE[1]")
set_input_delay 0.1 -clock "vclock" find(port,"BASE[2]")
set_input_delay 0.1 -clock "vclock" find(port,"BASE[3]")
set_input_delay 0.1 -clock "vclock" find(port,"BASE[4]")
set_input_delay 0.1 -clock "vclock" find(port,"BASE[5]")
set_input_delay 0.1 -clock "vclock" find(port,"BASE[6]")
set_input_delay 0.1 -clock "vclock" find(port,"BASE[7]")
set_input_delay 0.1 -clock "vclock" find(port,"BASE[8]")
set_input_delay 0.1 -clock "vclock" find(port,"BASE[9]")
set_input_delay 0.1 -clock "vclock" find(port,"BASE[10]")
set_input_delay 0.1 -clock "vclock" find(port,"BASE[11]")
set_input_delay 0.1 -clock "vclock" find(port,"BASE[12]")
set_input_delay 0.1 -clock "vclock" find(port,"BASE[13]")
set_input_delay 0.1 -clock "vclock" find(port,"BASE[14]")
set_input_delay 0.1 -clock "vclock" find(port,"BASE[15]")
set_input_delay 0.1 -clock "vclock" find(port,"BASE[16]")
set_input_delay 0.1 -clock "vclock" find(port,"BASE[17]")
set_input_delay 0.1 -clock "vclock" find(port,"BASE[18]")
set_input_delay 0.1 -clock "vclock" find(port,"BASE[19]")
set_output_delay 0.3 -clock "vclock" find(port,"WR_L")
set_output_delay 0.3 -clock "vclock" find(port,"SELECT_L")
set_output_delay 0.3 -clock "vclock" find(port,"ADR[0]")
set_output_delay 0.3 -clock "vclock" find(port,"ADR[1]")
set_output_delay 0.3 -clock "vclock" find(port,"ADR[2]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[0]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[1]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[2]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[3]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[4]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[5]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[6]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[7]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[8]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[9]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[10]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[11]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[12]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[13]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[14]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[15]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[16]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[17]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[18]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[19]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[20]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[21]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[22]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[23]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[24]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[25]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[26]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[27]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[28]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[29]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[30]")
set_output_delay 0.3 -clock "vclock" find(port,"DOUT[31]")
set_local_link_library {class.db}
set_wire_load_model  -name "10x10" -library "class"