songer.map.rpt

用VHDL语言写的

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; In-System Memory Content Editor Settings                                                                                                        ;
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; Instance Index ; Instance ID ; Width ; Depth ; Mode       ; Hierarchy Location                                                                  ;
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; 0              ; ROM1        ; 4     ; 256   ; Read/Write ; NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated ;
+----------------+-------------+-------+-------+------------+-------------------------------------------------------------------------------------+


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; Analysis & Synthesis Messages ;
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Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon May 19 22:29:28 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Songer -c Songer
Info: Found 2 design units, including 1 entities, in source file ../ToneTaba/ToneTaba.vhd
    Info: Found design unit 1: ToneTaba-one
    Info: Found entity 1: ToneTaba
Info: Found 2 design units, including 1 entities, in source file ../Speakra/Speakra.vhd
    Info: Found design unit 1: Speakera-one
    Info: Found entity 1: Speakera
Info: Found 2 design units, including 1 entities, in source file Songer.vhd
    Info: Found design unit 1: Songer-one
    Info: Found entity 1: Songer
Info: Found 2 design units, including 1 entities, in source file ../NoteTabs/NoteTabs.vhd
    Info: Found design unit 1: NoteTabs-one
    Info: Found entity 1: NoteTabs
Info: Elaborating entity "Songer" for the top level hierarchy
Info: Elaborating entity "NoteTabs" for hierarchy "NoteTabs:u1"
Warning: Using design file MUSIC.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: music-SYN
    Info: Found entity 1: MUSIC
Info: Elaborating entity "MUSIC" for hierarchy "NoteTabs:u1|MUSIC:u1"
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_k661.tdf
    Info: Found entity 1: altsyncram_k661
Info: Elaborating entity "altsyncram_k661" for hierarchy "NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ruj2.tdf
    Info: Found entity 1: altsyncram_ruj2
Info: Elaborating entity "altsyncram_ruj2" for hierarchy "NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1"
Info: Found 3 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd
    Info: Found design unit 1: sld_mod_ram_rom_pack
    Info: Found design unit 2: sld_mod_ram_rom-rtl
    Info: Found entity 1: sld_mod_ram_rom
Info: Elaborating entity "sld_mod_ram_rom" for hierarchy "NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2"
Info: Elaborated megafunction instantiation "NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2"
Info: Found 2 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd
    Info: Found design unit 1: sld_rom_sr-INFO_REG
    Info: Found entity 1: sld_rom_sr
Info: Elaborating entity "sld_rom_sr" for hierarchy "NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr"
Info: Elaborated megafunction instantiation "NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr", which is child of megafunction instantiation "NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2"
Info: Instantiated megafunction "NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2" with the following parameter:
    Info: Parameter "CVALUE" = "0000"
    Info: Parameter "IS_DATA_IN_RAM" = "1"
    Info: Parameter "IS_READABLE" = "1"
    Info: Parameter "NODE_NAME" = "1380928817"
    Info: Parameter "NUMWORDS" = "256"
    Info: Parameter "SHIFT_COUNT_BITS" = "3"
    Info: Parameter "WIDTH_WORD" = "4"
    Info: Parameter "WIDTHAD" = "8"
Info: Elaborating entity "ToneTaba" for hierarchy "ToneTaba:u2"
Warning (10631): VHDL Process Statement warning at ToneTaba.vhd(11): inferring latch(es) for signal or variable "Tone", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at ToneTaba.vhd(11): inferring latch(es) for signal or variable "CODE", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at ToneTaba.vhd(11): inferring latch(es) for signal or variable "HIGH", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "HIGH"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "CODE[0]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "CODE[1]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "CODE[2]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "CODE[3]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[0]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[1]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[2]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[3]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[4]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[5]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[6]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[7]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[8]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[9]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[10]"
Info: Elaborating entity "Speakera" for hierarchy "Speakera:u3"
Info: Found 6 design units, including 2 entities, in source file ../../altera/quartus60/libraries/megafunctions/sld_hub.vhd
    Info: Found design unit 1: HUB_PACK
    Info: Found design unit 2: JTAG_PACK
    Info: Found design unit 3: sld_hub-rtl
    Info: Found design unit 4: sld_jtag_state_machine-rtl
    Info: Found entity 1: sld_hub
    Info: Found entity 2: sld_jtag_state_machine
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst"
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "1"
    Info: Parameter "N_SEL_BITS" = "1"
    Info: Parameter "N_NODE_IR_BITS" = "5"
    Info: Parameter "NODE_INFO" = "00001000000110000110111000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone"
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/lpm_shiftreg.tdf
    Info: Found entity 1: lpm_shiftreg
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "1"
    Info: Parameter "N_SEL_BITS" = "1"
    Info: Parameter "N_NODE_IR_BITS" = "5"
    Info: Parameter "NODE_INFO" = "00001000000110000110111000000000"