songer.map.qmsg

用VHDL语言写的

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_rom_sr NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr " "Info: Elaborating entity \"sld_rom_sr\" for hierarchy \"NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\"" {  } { { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "\\ram_rom_logic_gen:name_gen:info_rom_sr" { Text "D:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 635 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborated megafunction instantiation \"NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\", which is child of megafunction instantiation \"NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 635 -1 0 } } { "db/altsyncram_k661.tdf" "" { Text "D:/EDA/Songer/db/altsyncram_k661.tdf" 35 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Instantiated megafunction \"NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "CVALUE 0000 " "Info: Parameter \"CVALUE\" = \"0000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IS_DATA_IN_RAM 1 " "Info: Parameter \"IS_DATA_IN_RAM\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IS_READABLE 1 " "Info: Parameter \"IS_READABLE\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NODE_NAME 1380928817 " "Info: Parameter \"NODE_NAME\" = \"1380928817\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS 256 " "Info: Parameter \"NUMWORDS\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SHIFT_COUNT_BITS 3 " "Info: Parameter \"SHIFT_COUNT_BITS\" = \"3\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_WORD 4 " "Info: Parameter \"WIDTH_WORD\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD 8 " "Info: Parameter \"WIDTHAD\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "db/altsyncram_k661.tdf" "" { Text "D:/EDA/Songer/db/altsyncram_k661.tdf" 35 2 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ToneTaba ToneTaba:u2 " "Info: Elaborating entity \"ToneTaba\" for hierarchy \"ToneTaba:u2\"" {  } { { "Songer.vhd" "u2" { Text "D:/EDA/Songer/Songer.vhd" 30 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "Tone ToneTaba.vhd(11) " "Warning (10631): VHDL Process Statement warning at ToneTaba.vhd(11): inferring latch(es) for signal or variable \"Tone\", which holds its previous value in one or more paths through the process" {  } { { "../ToneTaba/ToneTaba.vhd" "" { Text "D:/EDA/ToneTaba/ToneTaba.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "CODE ToneTaba.vhd(11) " "Warning (10631): VHDL Process Statement warning at ToneTaba.vhd(11): inferring latch(es) for signal or variable \"CODE\", which holds its previous value in one or more paths through the process" {  } { { "../ToneTaba/ToneTaba.vhd" "" { Text "D:/EDA/ToneTaba/ToneTaba.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "HIGH ToneTaba.vhd(11) " "Warning (10631): VHDL Process Statement warning at ToneTaba.vhd(11): inferring latch(es) for signal or variable \"HIGH\", which holds its previous value in one or more paths through the process" {  } { { "../ToneTaba/ToneTaba.vhd" "" { Text "D:/EDA/ToneTaba/ToneTaba.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "HIGH ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"HIGH\"" {  } { { "../ToneTaba/ToneTaba.vhd" "" { Text "D:/EDA/ToneTaba/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "CODE\[0\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"CODE\[0\]\"" {  } { { "../ToneTaba/ToneTaba.vhd" "" { Text "D:/EDA/ToneTaba/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "CODE\[1\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"CODE\[1\]\"" {  } { { "../ToneTaba/ToneTaba.vhd" "" { Text "D:/EDA/ToneTaba/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "CODE\[2\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"CODE\[2\]\"" {  } { { "../ToneTaba/ToneTaba.vhd" "" { Text "D:/EDA/ToneTaba/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "CODE\[3\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"CODE\[3\]\"" {  } { { "../ToneTaba/ToneTaba.vhd" "" { Text "D:/EDA/ToneTaba/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[0\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[0\]\"" {  } { { "../ToneTaba/ToneTaba.vhd" "" { Text "D:/EDA/ToneTaba/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[1\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[1\]\"" {  } { { "../ToneTaba/ToneTaba.vhd" "" { Text "D:/EDA/ToneTaba/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[2\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[2\]\"" {  } { { "../ToneTaba/ToneTaba.vhd" "" { Text "D:/EDA/ToneTaba/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[3\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[3\]\"" {  } { { "../ToneTaba/ToneTaba.vhd" "" { Text "D:/EDA/ToneTaba/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[4\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[4\]\"" {  } { { "../ToneTaba/ToneTaba.vhd" "" { Text "D:/EDA/ToneTaba/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[5\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[5\]\"" {  } { { "../ToneTaba/ToneTaba.vhd" "" { Text "D:/EDA/ToneTaba/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[6\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[6\]\"" {  } { { "../ToneTaba/ToneTaba.vhd" "" { Text "D:/EDA/ToneTaba/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[7\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[7\]\"" {  } { { "../ToneTaba/ToneTaba.vhd" "" { Text "D:/EDA/ToneTaba/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[8\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[8\]\"" {  } { { "../ToneTaba/ToneTaba.vhd" "" { Text "D:/EDA/ToneTaba/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[9\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[9\]\"" {  } { { "../ToneTaba/ToneTaba.vhd" "" { Text "D:/EDA/ToneTaba/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}