📄 songer.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK12MHZ register Speakera:u3\|\\GenSpkS:Count11\[2\] register Speakera:u3\|\\GenSpkS:Count11\[4\] 194.06 MHz 5.153 ns Internal " "Info: Clock \"CLK12MHZ\" has Internal fmax of 194.06 MHz between source register \"Speakera:u3\|\\GenSpkS:Count11\[2\]\" and destination register \"Speakera:u3\|\\GenSpkS:Count11\[4\]\" (period= 5.153 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.684 ns + Longest register register " "Info: + Longest register to register delay is 4.684 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Speakera:u3\|\\GenSpkS:Count11\[2\] 1 REG LC_X13_Y10_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y10_N7; Fanout = 4; REG Node = 'Speakera:u3\|\\GenSpkS:Count11\[2\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Speakera:u3|\GenSpkS:Count11[2] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.283 ns) + CELL(0.590 ns) 1.873 ns Speakera:u3\|Equal0~100 2 COMB LC_X13_Y9_N6 2 " "Info: 2: + IC(1.283 ns) + CELL(0.590 ns) = 1.873 ns; Loc. = LC_X13_Y9_N6; Fanout = 2; COMB Node = 'Speakera:u3\|Equal0~100'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.873 ns" { Speakera:u3|\GenSpkS:Count11[2] Speakera:u3|Equal0~100 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.169 ns Speakera:u3\|Equal0~103 3 COMB LC_X13_Y9_N7 11 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 2.169 ns; Loc. = LC_X13_Y9_N7; Fanout = 11; COMB Node = 'Speakera:u3\|Equal0~103'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { Speakera:u3|Equal0~100 Speakera:u3|Equal0~103 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.290 ns) + CELL(1.225 ns) 4.684 ns Speakera:u3\|\\GenSpkS:Count11\[4\] 4 REG LC_X13_Y10_N9 3 " "Info: 4: + IC(1.290 ns) + CELL(1.225 ns) = 4.684 ns; Loc. = LC_X13_Y10_N9; Fanout = 3; REG Node = 'Speakera:u3\|\\GenSpkS:Count11\[4\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.515 ns" { Speakera:u3|Equal0~103 Speakera:u3|\GenSpkS:Count11[4] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.929 ns ( 41.18 % ) " "Info: Total cell delay = 1.929 ns ( 41.18 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.755 ns ( 58.82 % ) " "Info: Total interconnect delay = 2.755 ns ( 58.82 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.684 ns" { Speakera:u3|\GenSpkS:Count11[2] Speakera:u3|Equal0~100 Speakera:u3|Equal0~103 Speakera:u3|\GenSpkS:Count11[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.684 ns" { Speakera:u3|\GenSpkS:Count11[2] Speakera:u3|Equal0~100 Speakera:u3|Equal0~103 Speakera:u3|\GenSpkS:Count11[4] } { 0.000ns 1.283ns 0.182ns 1.290ns } { 0.000ns 0.590ns 0.114ns 1.225ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.208 ns - Smallest " "Info: - Smallest clock skew is -0.208 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK12MHZ destination 7.983 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK12MHZ\" to destination register is 7.983 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK12MHZ 1 CLK PIN_28 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'CLK12MHZ'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK12MHZ } "NODE_NAME" } } { "Songer.vhd" "" { Text "D:/EDA/Songer/Songer.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns Speakera:u3\|\\DivideCLK:Count4\[2\] 2 REG LC_X27_Y10_N6 3 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N6; Fanout = 3; REG Node = 'Speakera:u3\|\\DivideCLK:Count4\[2\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.697 ns" { CLK12MHZ Speakera:u3|\DivideCLK:Count4[2] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(0.114 ns) 3.822 ns Speakera:u3\|LessThan0~39 3 COMB LC_X27_Y10_N5 16 " "Info: 3: + IC(0.542 ns) + CELL(0.114 ns) = 3.822 ns; Loc. = LC_X27_Y10_N5; Fanout = 16; COMB Node = 'Speakera:u3\|LessThan0~39'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.656 ns" { Speakera:u3|\DivideCLK:Count4[2] Speakera:u3|LessThan0~39 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1657 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.450 ns) + CELL(0.711 ns) 7.983 ns Speakera:u3\|\\GenSpkS:Count11\[4\] 4 REG LC_X13_Y10_N9 3 " "Info: 4: + IC(3.450 ns) + CELL(0.711 ns) = 7.983 ns; Loc. = LC_X13_Y10_N9; Fanout = 3; REG Node = 'Speakera:u3\|\\GenSpkS:Count11\[4\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.161 ns" { Speakera:u3|LessThan0~39 Speakera:u3|\GenSpkS:Count11[4] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.229 ns ( 40.45 % ) " "Info: Total cell delay = 3.229 ns ( 40.45 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.754 ns ( 59.55 % ) " "Info: Total interconnect delay = 4.754 ns ( 59.55 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.983 ns" { CLK12MHZ Speakera:u3|\DivideCLK:Count4[2] Speakera:u3|LessThan0~39 Speakera:u3|\GenSpkS:Count11[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.983 ns" { CLK12MHZ CLK12MHZ~out0 Speakera:u3|\DivideCLK:Count4[2] Speakera:u3|LessThan0~39 Speakera:u3|\GenSpkS:Count11[4] } { 0.000ns 0.000ns 0.762ns 0.542ns 3.450ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK12MHZ source 8.191 ns - Longest register " "Info: - Longest clock path from clock \"CLK12MHZ\" to source register is 8.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK12MHZ 1 CLK PIN_28 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'CLK12MHZ'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK12MHZ } "NODE_NAME" } } { "Songer.vhd" "" { Text "D:/EDA/Songer/Songer.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns Speakera:u3\|\\DivideCLK:Count4\[3\] 2 REG LC_X27_Y10_N4 2 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N4; Fanout = 2; REG Node = 'Speakera:u3\|\\DivideCLK:Count4\[3\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.697 ns" { CLK12MHZ Speakera:u3|\DivideCLK:Count4[3] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.572 ns) + CELL(0.292 ns) 4.030 ns Speakera:u3\|LessThan0~39 3 COMB LC_X27_Y10_N5 16 " "Info: 3: + IC(0.572 ns) + CELL(0.292 ns) = 4.030 ns; Loc. = LC_X27_Y10_N5; Fanout = 16; COMB Node = 'Speakera:u3\|LessThan0~39'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.864 ns" { Speakera:u3|\DivideCLK:Count4[3] Speakera:u3|LessThan0~39 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1657 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.450 ns) + CELL(0.711 ns) 8.191 ns Speakera:u3\|\\GenSpkS:Count11\[2\] 4 REG LC_X13_Y10_N7 4 " "Info: 4: + IC(3.450 ns) + CELL(0.711 ns) = 8.191 ns; Loc. = LC_X13_Y10_N7; Fanout = 4; REG Node = 'Speakera:u3\|\\GenSpkS:Count11\[2\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.161 ns" { Speakera:u3|LessThan0~39 Speakera:u3|\GenSpkS:Count11[2] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.407 ns ( 41.59 % ) " "Info: Total cell delay = 3.407 ns ( 41.59 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.784 ns ( 58.41 % ) " "Info: Total interconnect delay = 4.784 ns ( 58.41 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.191 ns" { CLK12MHZ Speakera:u3|\DivideCLK:Count4[3] Speakera:u3|LessThan0~39 Speakera:u3|\GenSpkS:Count11[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.191 ns" { CLK12MHZ CLK12MHZ~out0 Speakera:u3|\DivideCLK:Count4[3] Speakera:u3|LessThan0~39 Speakera:u3|\GenSpkS:Count11[2] } { 0.000ns 0.000ns 0.762ns 0.572ns 3.450ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.983 ns" { CLK12MHZ Speakera:u3|\DivideCLK:Count4[2] Speakera:u3|LessThan0~39 Speakera:u3|\GenSpkS:Count11[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.983 ns" { CLK12MHZ CLK12MHZ~out0 Speakera:u3|\DivideCLK:Count4[2] Speakera:u3|LessThan0~39 Speakera:u3|\GenSpkS:Count11[4] } { 0.000ns 0.000ns 0.762ns 0.542ns 3.450ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.191 ns" { CLK12MHZ Speakera:u3|\DivideCLK:Count4[3] Speakera:u3|LessThan0~39 Speakera:u3|\GenSpkS:Count11[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.191 ns" { CLK12MHZ CLK12MHZ~out0 Speakera:u3|\DivideCLK:Count4[3] Speakera:u3|LessThan0~39 Speakera:u3|\GenSpkS:Count11[2] } { 0.000ns 0.000ns 0.762ns 0.572ns 3.450ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.684 ns" { Speakera:u3|\GenSpkS:Count11[2] Speakera:u3|Equal0~100 Speakera:u3|Equal0~103 Speakera:u3|\GenSpkS:Count11[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.684 ns" { Speakera:u3|\GenSpkS:Count11[2] Speakera:u3|Equal0~100 Speakera:u3|Equal0~103 Speakera:u3|\GenSpkS:Count11[4] } { 0.000ns 1.283ns 0.182ns 1.290ns } { 0.000ns 0.590ns 0.114ns 1.225ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.983 ns" { CLK12MHZ Speakera:u3|\DivideCLK:Count4[2] Speakera:u3|LessThan0~39 Speakera:u3|\GenSpkS:Count11[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.983 ns" { CLK12MHZ CLK12MHZ~out0 Speakera:u3|\DivideCLK:Count4[2] Speakera:u3|LessThan0~39 Speakera:u3|\GenSpkS:Count11[4] } { 0.000ns 0.000ns 0.762ns 0.542ns 3.450ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.191 ns" { CLK12MHZ Speakera:u3|\DivideCLK:Count4[3] Speakera:u3|LessThan0~39 Speakera:u3|\GenSpkS:Count11[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.191 ns" { CLK12MHZ CLK12MHZ~out0 Speakera:u3|\DivideCLK:Count4[3] Speakera:u3|LessThan0~39 Speakera:u3|\GenSpkS:Count11[2] } { 0.000ns 0.000ns 0.762ns 0.572ns 3.450ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.711ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK8HZ memory NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|altsyncram_ruj2:altsyncram1\|ram_block3a1~porta_datain_reg0 memory NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|altsyncram_ruj2:altsyncram1\|ram_block3a1~porta_memory_reg0 197.01 MHz 5.076 ns Internal " "Info: Clock \"CLK8HZ\" has Internal fmax of 197.01 MHz between source memory \"NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|altsyncram_ruj2:altsyncram1\|ram_block3a1~porta_datain_reg0\" and destination memory \"NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|altsyncram_ruj2:altsyncram1\|ram_block3a1~porta_memory_reg0\" (period= 5.076 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|altsyncram_ruj2:altsyncram1\|ram_block3a1~porta_datain_reg0 1 MEM M4K_X17_Y10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y10; Fanout = 1; MEM Node = 'NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|altsyncram_ruj2:altsyncram1\|ram_block3a1~porta_datain_reg0'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_ruj2.tdf" "" { Text "D:/EDA/Songer/db/altsyncram_ruj2.tdf" 80 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|altsyncram_ruj2:altsyncram1\|ram_block3a1~porta_memory_reg0 2 MEM M4K_X17_Y10 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X17_Y10; Fanout = 0; MEM Node = 'NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|altsyncram_ruj2:altsyncram1\|ram_block3a1~porta_memory_reg0'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_datain_reg0 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_ruj2.tdf" "" { Text "D:/EDA/Songer/db/altsyncram_ruj2.tdf" 80 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_datain_reg0 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_memory_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.319 ns" { NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_datain_reg0 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns - Smallest " "Info: - Smallest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK8HZ destination 2.941 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLK8HZ\" to destination memory is 2.941 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK8HZ 1 CLK PIN_29 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'CLK8HZ'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK8HZ } "NODE_NAME" } } { "Songer.vhd" "" { Text "D:/EDA/Songer/Songer.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.764 ns) + CELL(0.708 ns) 2.941 ns NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|altsyncram_ruj2:altsyncram1\|ram_block3a1~porta_memory_reg0 2 MEM M4K_X17_Y10 0 " "Info: 2: + IC(0.764 ns) + CELL(0.708 ns) = 2.941 ns; Loc. = M4K_X17_Y10; Fanout = 0; MEM Node = 'NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|altsyncram_ruj2:altsyncram1\|ram_block3a1~porta_memory_reg0'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.472 ns" { CLK8HZ NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_ruj2.tdf" "" { Text "D:/EDA/Songer/db/altsyncram_ruj2.tdf" 80 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns ( 74.02 % ) " "Info: Total cell delay = 2.177 ns ( 74.02 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.764 ns ( 25.98 % ) " "Info: Total interconnect delay = 0.764 ns ( 25.98 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.941 ns" { CLK8HZ NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_memory_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.941 ns" { CLK8HZ CLK8HZ~out0 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_memory_reg0 } { 0.000ns 0.000ns 0.764ns } { 0.000ns 1.469ns 0.708ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK8HZ source 2.955 ns - Longest memory " "Info: - Longest clock path from clock \"CLK8HZ\" to source memory is 2.955 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK8HZ 1 CLK PIN_29 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'CLK8HZ'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK8HZ } "NODE_NAME" } } { "Songer.vhd" "" { Text "D:/EDA/Songer/Songer.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.764 ns) + CELL(0.722 ns) 2.955 ns NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|altsyncram_ruj2:altsyncram1\|ram_block3a1~porta_datain_reg0 2 MEM M4K_X17_Y10 1 " "Info: 2: + IC(0.764 ns) + CELL(0.722 ns) = 2.955 ns; Loc. = M4K_X17_Y10; Fanout = 1; MEM Node = 'NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|altsyncram_ruj2:altsyncram1\|ram_block3a1~porta_datain_reg0'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.486 ns" { CLK8HZ NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_ruj2.tdf" "" { Text "D:/EDA/Songer/db/altsyncram_ruj2.tdf" 80 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 74.15 % ) " "Info: Total cell delay = 2.191 ns ( 74.15 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.764 ns ( 25.85 % ) " "Info: Total interconnect delay = 0.764 ns ( 25.85 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.955 ns" { CLK8HZ NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_datain_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.955 ns" { CLK8HZ CLK8HZ~out0 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_datain_reg0 } { 0.000ns 0.000ns 0.764ns } { 0.000ns 1.469ns 0.722ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.941 ns" { CLK8HZ NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_memory_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.941 ns" { CLK8HZ CLK8HZ~out0 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_memory_reg0 } { 0.000ns 0.000ns 0.764ns } { 0.000ns 1.469ns 0.708ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.955 ns" { CLK8HZ NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_datain_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.955 ns" { CLK8HZ CLK8HZ~out0 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_datain_reg0 } { 0.000ns 0.000ns 0.764ns } { 0.000ns 1.469ns 0.722ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" { } { { "db/altsyncram_ruj2.tdf" "" { Text "D:/EDA/Songer/db/altsyncram_ruj2.tdf" 80 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" { } { { "db/altsyncram_ruj2.tdf" "" { Text "D:/EDA/Songer/db/altsyncram_ruj2.tdf" 80 2 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_datain_reg0 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_memory_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.319 ns" { NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_datain_reg0 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.941 ns" { CLK8HZ NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_memory_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.941 ns" { CLK8HZ CLK8HZ~out0 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_memory_reg0 } { 0.000ns 0.000ns 0.764ns } { 0.000ns 1.469ns 0.708ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.955 ns" { CLK8HZ NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_datain_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.955 ns" { CLK8HZ CLK8HZ~out0 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|altsyncram_ruj2:altsyncram1|ram_block3a1~porta_datain_reg0 } { 0.000ns 0.000ns 0.764ns } { 0.000ns 1.469ns 0.722ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\] register sld_hub:sld_hub_inst\|hub_tdo 137.1 MHz 7.294 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 137.1 MHz between source register \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 7.294 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.386 ns + Longest register register " "Info: + Longest register to register delay is 3.386 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\] 1 REG LC_X20_Y10_N2 29 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y10_N2; Fanout = 29; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.739 ns) + CELL(0.114 ns) 1.853 ns sld_hub:sld_hub_inst\|hub_tdo~542 2 COMB LC_X21_Y9_N9 1 " "Info: 2: + IC(1.739 ns) + CELL(0.114 ns) = 1.853 ns; Loc. = LC_X21_Y9_N9; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~542'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.853 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|hub_tdo~542 } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.224 ns) + CELL(0.309 ns) 3.386 ns sld_hub:sld_hub_inst\|hub_tdo 3 REG LC_X20_Y10_N1 1 " "Info: 3: + IC(1.224 ns) + CELL(0.309 ns) = 3.386 ns; Loc. = LC_X20_Y10_N1; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.533 ns" { sld_hub:sld_hub_inst|hub_tdo~542 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.423 ns ( 12.49 % ) " "Info: Total cell delay = 0.423 ns ( 12.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.963 ns ( 87.51 % ) " "Info: Total interconnect delay = 2.963 ns ( 87.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.386 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|hub_tdo~542 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.386 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|hub_tdo~542 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.739ns 1.224ns } { 0.000ns 0.114ns 0.309ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.310 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.310 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 117 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 117; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.599 ns) + CELL(0.711 ns) 5.310 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X20_Y10_N1 1 " "Info: 2: + IC(4.599 ns) + CELL(0.711 ns) = 5.310 ns; Loc. = LC_X20_Y10_N1; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.39 % ) " "Info: Total cell delay = 0.711 ns ( 13.39 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.599 ns ( 86.61 % ) " "Info: Total interconnect delay = 4.599 ns ( 86.61 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.599ns } { 0.000ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.310 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.310 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 117 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 117; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.599 ns) + CELL(0.711 ns) 5.310 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\] 2 REG LC_X20_Y10_N2 29 " "Info: 2: + IC(4.599 ns) + CELL(0.711 ns) = 5.310 ns; Loc. = LC_X20_Y10_N2; Fanout = 29; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.39 % ) " "Info: Total cell delay = 0.711 ns ( 13.39 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.599 ns ( 86.61 % ) " "Info: Total interconnect delay = 4.599 ns ( 86.61 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } { 0.000ns 4.599ns } { 0.000ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.599ns } { 0.000ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } { 0.000ns 4.599ns } { 0.000ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.386 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|hub_tdo~542 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.386 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|hub_tdo~542 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.739ns 1.224ns } { 0.000ns 0.114ns 0.309ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.599ns } { 0.000ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } { 0.000ns 4.599ns } { 0.000ns 0.711ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
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