speakra.vhd

用VHDL语言写的

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Speakera IS
	PORT ( clk : IN STD_LOGIC;
			Tone : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
			SpkS : OUT STD_LOGIC );
	END;
ARCHITECTURE one OF Speakera IS
	SIGNAL PreCLK, FullSpkS : STD_LOGIC;
BEGIN
	DivideCLK : PROCESS(clk)
	VARIABLE Count4 : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
	BEGIN
		PreCLK <= '0';
		IF Count4>11 THEN PreCLK <= '1';Count4 := "0000";
		ELSIF clk'EVENT AND clk = '1' THEN Count4 := Count4 + 1;
		END IF;
	END PROCESS;
	GenSpkS : PROCESS(PreCLK, Tone)
		VARIABLE Count11 : STD_LOGIC_VECTOR (10 DOWNTO 0);
	BEGIN
		IF PreCLK'EVENT AND PreCLK = '1' THEN
		IF Count11 = 16#7FF# THEN Count11 := Tone ; FullSpkS <='1';
			ELSE Count11 := Count11 +1; FullSpkS <= '0'; END IF;
			END IF;
		END PROCESS;
	DelaySpkS : PROCESS(FullSpkS)
		VARIABLE Count2 : STD_LOGIC;
	BEGIN
		IF FullSpkS'EVENT AND FullSpkS ='1' THEN Count2 := NOT Count2;
			IF Count2 = '1' THEN SpkS <= '1';
			ELSE SpkS <= '0'; END IF;
		END IF;
		END PROCESS;
	END;