config_dac_modelsim.xrf

Verilog实现 spi接口的FPGA实现 通过仿真

vendor_name = ModelSim
source_file = 1, D:/altera/71/config_dac/config_dac.v
source_file = 1, D:/altera/71/config_dac/ad9777_spi_interface.v
source_file = 1, D:/altera/71/config_dac/test_config_dac.v
design_name = config_dac
instance = comp, \data_to_send[2] , data_to_send[2], config_dac, 1
instance = comp, \data_to_send[1] , data_to_send[1], config_dac, 1
instance = comp, \data_to_send[2]~658 , data_to_send[2]~658, config_dac, 1
instance = comp, \data_to_send[0] , data_to_send[0], config_dac, 1
instance = comp, \data_to_send[1]~659 , data_to_send[1]~659, config_dac, 1
instance = comp, \data_to_send[0]~660 , data_to_send[0]~660, config_dac, 1
instance = comp, \wdata[2] , wdata[2], config_dac, 1
instance = comp, \waddr[2] , waddr[2], config_dac, 1
instance = comp, \bit_transfered[1] , bit_transfered[1], config_dac, 1
instance = comp, \wdata[1] , wdata[1], config_dac, 1
instance = comp, \waddr[1] , waddr[1], config_dac, 1
instance = comp, \bit_transfered~558 , bit_transfered~558, config_dac, 1
instance = comp, \data_to_send~908 , data_to_send~908, config_dac, 1
instance = comp, \wdata[0] , wdata[0], config_dac, 1
instance = comp, \waddr[0] , waddr[0], config_dac, 1
instance = comp, \wr_data[2]~I , wr_data[2], config_dac, 1
instance = comp, \wr_rd_addr[2]~I , wr_rd_addr[2], config_dac, 1
instance = comp, \wr_data[1]~I , wr_data[1], config_dac, 1
instance = comp, \wr_rd_addr[1]~I , wr_rd_addr[1], config_dac, 1
instance = comp, \wr_data[0]~I , wr_data[0], config_dac, 1
instance = comp, \wr_rd_addr[0]~I , wr_rd_addr[0], config_dac, 1
instance = comp, \wdata[1]~feeder , wdata[1]~feeder, config_dac, 1
instance = comp, \waddr[0]~feeder , waddr[0]~feeder, config_dac, 1
instance = comp, \clk~I , clk, config_dac, 1
instance = comp, \clk~clkctrl , clk~clkctrl, config_dac, 1
instance = comp, \spi_sdo~I , spi_sdo, config_dac, 1
instance = comp, \sdo_in~feeder , sdo_in~feeder, config_dac, 1
instance = comp, \data_received[0]~feeder , data_received[0]~feeder, config_dac, 1
instance = comp, \wr_en~I , wr_en, config_dac, 1
instance = comp, \rd_en~I , rd_en, config_dac, 1
instance = comp, \always1~0 , always1~0, config_dac, 1
instance = comp, \sck_count~51 , sck_count~51, config_dac, 1
instance = comp, \sck_count[1] , sck_count[1], config_dac, 1
instance = comp, \Equal1~125 , Equal1~125, config_dac, 1
instance = comp, \Selector4~62 , Selector4~62, config_dac, 1
instance = comp, \resetb~I , resetb, config_dac, 1
instance = comp, \resetb~clkctrl , resetb~clkctrl, config_dac, 1
instance = comp, \main_state.START , main_state.START, config_dac, 1
instance = comp, \bit_transfered~557 , bit_transfered~557, config_dac, 1
instance = comp, \bit_transfered[7]~550 , bit_transfered[7]~550, config_dac, 1
instance = comp, \bit_transfered[2] , bit_transfered[2], config_dac, 1
instance = comp, \bit_transfered~556 , bit_transfered~556, config_dac, 1
instance = comp, \bit_transfered[3] , bit_transfered[3], config_dac, 1
instance = comp, \bit_transfered~555 , bit_transfered~555, config_dac, 1
instance = comp, \bit_transfered[4] , bit_transfered[4], config_dac, 1
instance = comp, \bit_transfered~554 , bit_transfered~554, config_dac, 1
instance = comp, \bit_transfered[5] , bit_transfered[5], config_dac, 1
instance = comp, \bit_transfered~553 , bit_transfered~553, config_dac, 1
instance = comp, \bit_transfered[6] , bit_transfered[6], config_dac, 1
instance = comp, \bit_transfered~549 , bit_transfered~549, config_dac, 1
instance = comp, \bit_transfered[7] , bit_transfered[7], config_dac, 1
instance = comp, \Selector1~58 , Selector1~58, config_dac, 1
instance = comp, \bit_transfered~551 , bit_transfered~551, config_dac, 1
instance = comp, \bit_transfered[8] , bit_transfered[8], config_dac, 1
instance = comp, \Selector1~59 , Selector1~59, config_dac, 1
instance = comp, \main_state.DATA , main_state.DATA, config_dac, 1
instance = comp, \main_state.STOP~49 , main_state.STOP~49, config_dac, 1
instance = comp, \main_state.STOP , main_state.STOP, config_dac, 1
instance = comp, \Selector3~18 , Selector3~18, config_dac, 1
instance = comp, \main_state.IDLE , main_state.IDLE, config_dac, 1
instance = comp, \sck_count~50 , sck_count~50, config_dac, 1
instance = comp, \sck_count[0] , sck_count[0], config_dac, 1
instance = comp, \Equal1~126 , Equal1~126, config_dac, 1
instance = comp, \data_received[0] , data_received[0], config_dac, 1
instance = comp, \rd_data[0]~reg0feeder , rd_data[0]~reg0feeder, config_dac, 1
instance = comp, \read_flag~27 , read_flag~27, config_dac, 1
instance = comp, \always13~2 , always13~2, config_dac, 1
instance = comp, \rd_data[0]~reg0 , rd_data[0]~reg0, config_dac, 1
instance = comp, \data_received[1]~feeder , data_received[1]~feeder, config_dac, 1
instance = comp, \data_received[1] , data_received[1], config_dac, 1
instance = comp, \rd_data[1]~reg0feeder , rd_data[1]~reg0feeder, config_dac, 1
instance = comp, \rd_data[1]~reg0 , rd_data[1]~reg0, config_dac, 1
instance = comp, \data_received[2]~feeder , data_received[2]~feeder, config_dac, 1
instance = comp, \data_received[2] , data_received[2], config_dac, 1
instance = comp, \rd_data[2]~reg0feeder , rd_data[2]~reg0feeder, config_dac, 1
instance = comp, \rd_data[2]~reg0 , rd_data[2]~reg0, config_dac, 1
instance = comp, \data_received[3]~feeder , data_received[3]~feeder, config_dac, 1
instance = comp, \data_received[3] , data_received[3], config_dac, 1
instance = comp, \rd_data[3]~reg0feeder , rd_data[3]~reg0feeder, config_dac, 1
instance = comp, \rd_data[3]~reg0 , rd_data[3]~reg0, config_dac, 1
instance = comp, \data_received[4]~feeder , data_received[4]~feeder, config_dac, 1
instance = comp, \data_received[4] , data_received[4], config_dac, 1
instance = comp, \rd_data[4]~reg0feeder , rd_data[4]~reg0feeder, config_dac, 1
instance = comp, \rd_data[4]~reg0 , rd_data[4]~reg0, config_dac, 1
instance = comp, \data_received[5]~feeder , data_received[5]~feeder, config_dac, 1
instance = comp, \data_received[5] , data_received[5], config_dac, 1
instance = comp, \rd_data[5]~reg0feeder , rd_data[5]~reg0feeder, config_dac, 1
instance = comp, \rd_data[5]~reg0 , rd_data[5]~reg0, config_dac, 1
instance = comp, \data_received[6]~feeder , data_received[6]~feeder, config_dac, 1
instance = comp, \data_received[6] , data_received[6], config_dac, 1
instance = comp, \rd_data[6]~reg0 , rd_data[6]~reg0, config_dac, 1
instance = comp, \data_received[7]~feeder , data_received[7]~feeder, config_dac, 1
instance = comp, \data_received[7] , data_received[7], config_dac, 1
instance = comp, \rd_data[7]~reg0feeder , rd_data[7]~reg0feeder, config_dac, 1
instance = comp, \rd_data[7]~reg0 , rd_data[7]~reg0, config_dac, 1
instance = comp, \rd_data_valid~reg0 , rd_data_valid~reg0, config_dac, 1
instance = comp, \busy~reg0feeder , busy~reg0feeder, config_dac, 1
instance = comp, \busy~reg0 , busy~reg0, config_dac, 1
instance = comp, \spi_ncs~83 , spi_ncs~83, config_dac, 1
instance = comp, \spi_ncs~84 , spi_ncs~84, config_dac, 1
instance = comp, \spi_ncs~reg0 , spi_ncs~reg0, config_dac, 1
instance = comp, \wr_data[7]~I , wr_data[7], config_dac, 1
instance = comp, \wdata[7]~feeder , wdata[7]~feeder, config_dac, 1
instance = comp, \wdata[7] , wdata[7], config_dac, 1
instance = comp, \bit_transfered~552 , bit_transfered~552, config_dac, 1
instance = comp, \bit_transfered[0] , bit_transfered[0], config_dac, 1
instance = comp, \Selector2~26 , Selector2~26, config_dac, 1
instance = comp, \main_state.INSTRUCTION , main_state.INSTRUCTION, config_dac, 1
instance = comp, \always9~0 , always9~0, config_dac, 1
instance = comp, \wr_data[6]~I , wr_data[6], config_dac, 1
instance = comp, \wdata[6]~feeder , wdata[6]~feeder, config_dac, 1
instance = comp, \wdata[6] , wdata[6], config_dac, 1
instance = comp, \wr_data[5]~I , wr_data[5], config_dac, 1
instance = comp, \wdata[5] , wdata[5], config_dac, 1
instance = comp, \wr_data[4]~I , wr_data[4], config_dac, 1
instance = comp, \wdata[4] , wdata[4], config_dac, 1
instance = comp, \wr_data[3]~I , wr_data[3], config_dac, 1
instance = comp, \wdata[3]~feeder , wdata[3]~feeder, config_dac, 1
instance = comp, \wdata[3] , wdata[3], config_dac, 1
instance = comp, \always9~1 , always9~1, config_dac, 1
instance = comp, \data_to_send[3]~657 , data_to_send[3]~657, config_dac, 1
instance = comp, \wr_rd_addr[3]~I , wr_rd_addr[3], config_dac, 1
instance = comp, \waddr[3]~feeder , waddr[3]~feeder, config_dac, 1
instance = comp, \waddr[3] , waddr[3], config_dac, 1
instance = comp, \data_to_send[7]~905 , data_to_send[7]~905, config_dac, 1
instance = comp, \data_to_send[3] , data_to_send[3], config_dac, 1
instance = comp, \data_to_send[4]~656 , data_to_send[4]~656, config_dac, 1
instance = comp, \wr_rd_addr[4]~I , wr_rd_addr[4], config_dac, 1
instance = comp, \waddr[4] , waddr[4], config_dac, 1
instance = comp, \data_to_send[4] , data_to_send[4], config_dac, 1
instance = comp, \data_to_send~907 , data_to_send~907, config_dac, 1
instance = comp, \data_to_send[5] , data_to_send[5], config_dac, 1
instance = comp, \data_to_send~906 , data_to_send~906, config_dac, 1
instance = comp, \data_to_send[6] , data_to_send[6], config_dac, 1
instance = comp, \data_to_send[7]~655 , data_to_send[7]~655, config_dac, 1
instance = comp, \data_to_send[7] , data_to_send[7], config_dac, 1
instance = comp, \bit_transfered[7]~548 , bit_transfered[7]~548, config_dac, 1
instance = comp, \spi_sck~33 , spi_sck~33, config_dac, 1
instance = comp, \spi_sck~reg0 , spi_sck~reg0, config_dac, 1
instance = comp, \rd_data[0]~I , rd_data[0], config_dac, 1
instance = comp, \rd_data[1]~I , rd_data[1], config_dac, 1
instance = comp, \rd_data[2]~I , rd_data[2], config_dac, 1
instance = comp, \rd_data[3]~I , rd_data[3], config_dac, 1
instance = comp, \rd_data[4]~I , rd_data[4], config_dac, 1
instance = comp, \rd_data[5]~I , rd_data[5], config_dac, 1
instance = comp, \rd_data[6]~I , rd_data[6], config_dac, 1
instance = comp, \rd_data[7]~I , rd_data[7], config_dac, 1
instance = comp, \rd_data_valid~I , rd_data_valid, config_dac, 1
instance = comp, \busy~I , busy, config_dac, 1
instance = comp, \spi_ncs~I , spi_ncs, config_dac, 1
instance = comp, \spi_sdio~I , spi_sdio, config_dac, 1
instance = comp, \spi_sck~I , spi_sck, config_dac, 1