k20test.tan.qmsg

只需要FPGA两个通用管脚

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\] register sld_hub:sld_hub_inst\|hub_tdo 85.22 MHz 11.734 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 85.22 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 11.734 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.601 ns + Longest register register " "Info: + Longest register to register delay is 5.601 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\] 1 REG LCFF_X36_Y14_N27 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X36_Y14_N27; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.514 ns) + CELL(0.539 ns) 2.053 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\]~209 2 COMB LCCOMB_X38_Y15_N6 3 " "Info: 2: + IC(1.514 ns) + CELL(0.539 ns) = 2.053 ns; Loc. = LCCOMB_X38_Y15_N6; Fanout = 3; COMB Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\]~209'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.053 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]~209 } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.409 ns) + CELL(0.650 ns) 3.112 ns sld_hub:sld_hub_inst\|hub_tdo~580 3 COMB LCCOMB_X38_Y15_N4 1 " "Info: 3: + IC(0.409 ns) + CELL(0.650 ns) = 3.112 ns; Loc. = LCCOMB_X38_Y15_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~580'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.059 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]~209 sld_hub:sld_hub_inst|hub_tdo~580 } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.363 ns) + CELL(0.624 ns) 4.099 ns sld_hub:sld_hub_inst\|hub_tdo~581 4 COMB LCCOMB_X38_Y15_N18 1 " "Info: 4: + IC(0.363 ns) + CELL(0.624 ns) = 4.099 ns; Loc. = LCCOMB_X38_Y15_N18; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~581'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.987 ns" { sld_hub:sld_hub_inst|hub_tdo~580 sld_hub:sld_hub_inst|hub_tdo~581 } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.743 ns) + CELL(0.651 ns) 5.493 ns sld_hub:sld_hub_inst\|hub_tdo~582 5 COMB LCCOMB_X38_Y15_N10 1 " "Info: 5: + IC(0.743 ns) + CELL(0.651 ns) = 5.493 ns; Loc. = LCCOMB_X38_Y15_N10; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~582'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.394 ns" { sld_hub:sld_hub_inst|hub_tdo~581 sld_hub:sld_hub_inst|hub_tdo~582 } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 5.601 ns sld_hub:sld_hub_inst\|hub_tdo 6 REG LCFF_X38_Y15_N11 2 " "Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 5.601 ns; Loc. = LCFF_X38_Y15_N11; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { sld_hub:sld_hub_inst|hub_tdo~582 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.572 ns ( 45.92 % ) " "Info: Total cell delay = 2.572 ns ( 45.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.029 ns ( 54.08 % ) " "Info: Total interconnect delay = 3.029 ns ( 54.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.601 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]~209 sld_hub:sld_hub_inst|hub_tdo~580 sld_hub:sld_hub_inst|hub_tdo~581 sld_hub:sld_hub_inst|hub_tdo~582 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "5.601 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]~209 sld_hub:sld_hub_inst|hub_tdo~580 sld_hub:sld_hub_inst|hub_tdo~581 sld_hub:sld_hub_inst|hub_tdo~582 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.514ns 0.409ns 0.363ns 0.743ns 0.000ns } { 0.000ns 0.539ns 0.650ns 0.624ns 0.651ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.002 ns - Smallest " "Info: - Smallest clock skew is -0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 6.572 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 6.572 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y14_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.833 ns) + CELL(0.000 ns) 4.833 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G11 127 " "Info: 2: + IC(4.833 ns) + CELL(0.000 ns) = 4.833 ns; Loc. = CLKCTRL_G11; Fanout = 127; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.833 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.666 ns) 6.572 ns sld_hub:sld_hub_inst\|hub_tdo 3 REG LCFF_X38_Y15_N11 2 " "Info: 3: + IC(1.073 ns) + CELL(0.666 ns) = 6.572 ns; Loc. = LCFF_X38_Y15_N11; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.739 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 10.13 % ) " "Info: Total cell delay = 0.666 ns ( 10.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.906 ns ( 89.87 % ) " "Info: Total interconnect delay = 5.906 ns ( 89.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.572 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "6.572 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.833ns 1.073ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 6.574 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 6.574 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y14_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.833 ns) + CELL(0.000 ns) 4.833 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G11 127 " "Info: 2: + IC(4.833 ns) + CELL(0.000 ns) = 4.833 ns; Loc. = CLKCTRL_G11; Fanout = 127; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.833 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.075 ns) + CELL(0.666 ns) 6.574 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\] 3 REG LCFF_X36_Y14_N27 4 " "Info: 3: + IC(1.075 ns) + CELL(0.666 ns) = 6.574 ns; Loc. = LCFF_X36_Y14_N27; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.741 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 10.13 % ) " "Info: Total cell delay = 0.666 ns ( 10.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.908 ns ( 89.87 % ) " "Info: Total interconnect delay = 5.908 ns ( 89.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.574 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "6.574 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } { 0.000ns 4.833ns 1.075ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.572 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "6.572 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.833ns 1.073ns } { 0.000ns 0.000ns 0.666ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.574 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "6.574 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } { 0.000ns 4.833ns 1.075ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "../../altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "../../altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.601 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]~209 sld_hub:sld_hub_inst|hub_tdo~580 sld_hub:sld_hub_inst|hub_tdo~581 sld_hub:sld_hub_inst|hub_tdo~582 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "5.601 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]~209 sld_hub:sld_hub_inst|hub_tdo~580 sld_hub:sld_hub_inst|hub_tdo~581 sld_hub:sld_hub_inst|hub_tdo~582 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.514ns 0.409ns 0.363ns 0.743ns 0.000ns } { 0.000ns 0.539ns 0.650ns 0.624ns 0.651ns 0.108ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.572 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "6.572 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.833ns 1.073ns } { 0.000ns 0.000ns 0.666ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.574 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "6.574 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } { 0.000ns 4.833ns 1.075ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 register TENBASET_TxD:inst\|counter\[0\] register TENBASET_TxD:inst\|counter\[0\] 499 ps " "Info: Minimum slack time is 499 ps for clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" between source register \"TENBASET_TxD:inst\|counter\[0\]\" and destination register \"TENBASET_TxD:inst\|counter\[0\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.501 ns + Shortest register register " "Info: + Shortest register to register delay is 0.501 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns TENBASET_TxD:inst\|counter\[0\] 1 REG LCFF_X42_Y13_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X42_Y13_N9; Fanout = 4; REG Node = 'TENBASET_TxD:inst\|counter\[0\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { TENBASET_TxD:inst|counter[0] } "NODE_NAME" } } { "k20test.v" "" { Text "F:/NIOS2/k21test/k20test.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.393 ns) 0.393 ns TENBASET_TxD:inst\|counter\[0\]~140 2 COMB LCCOMB_X42_Y13_N8 1 " "Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X42_Y13_N8; Fanout = 1; COMB Node = 'TENBASET_TxD:inst\|counter\[0\]~140'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.393 ns" { TENBASET_TxD:inst|counter[0] TENBASET_TxD:inst|counter[0]~140 } "NODE_NAME" } } { "k20test.v" "" { Text "F:/NIOS2/k21test/k20test.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.501 ns TENBASET_TxD:inst\|counter\[0\] 3 REG LCFF_X42_Y13_N9 4 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.501 ns; Loc. = LCFF_X42_Y13_N9; Fanout = 4; REG Node = 'TENBASET_TxD:inst\|counter\[0\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { TENBASET_TxD:inst|counter[0]~140 TENBASET_TxD:inst|counter[0] } "NODE_NAME" } } { "k20test.v" "" { Text "F:/NIOS2/k21test/k20test.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.501 ns ( 100.00 % ) " "Info: Total cell delay = 0.501 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.501 ns" { TENBASET_TxD:inst|counter[0] TENBASET_TxD:inst|counter[0]~140 TENBASET_TxD:inst|counter[0] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "0.501 ns" { TENBASET_TxD:inst|counter[0] TENBASET_TxD:inst|counter[0]~140 TENBASET_TxD:inst|counter[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.002 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.002 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.616 ns " "Info: + Latch edge is -2.616 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst1\|altpll:altpll_component\|_clk0 50.000 ns -2.616 ns  50 " "Info: Clock period of Destination clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is 50.000 ns with  offset of -2.616 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.616 ns " "Info: - Launch edge is -2.616 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst1\|altpll:altpll_component\|_clk0 50.000 ns -2.616 ns  50 " "Info: Clock period of Source clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is 50.000 ns with  offset of -2.616 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 destination 2.758 ns + Longest register " "Info: + Longest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.758 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.005 ns) + CELL(0.000 ns) 1.005 ns altpll0:inst1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 113 " "Info: 2: + IC(1.005 ns) + CELL(0.000 ns) = 1.005 ns; Loc. = CLKCTRL_G3; Fanout = 113; COMB Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.005 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.087 ns) + CELL(0.666 ns) 2.758 ns TENBASET_TxD:inst\|counter\[0\] 3 REG LCFF_X42_Y13_N9 4 " "Info: 3: + IC(1.087 ns) + CELL(0.666 ns) = 2.758 ns; Loc. = LCFF_X42_Y13_N9; Fanout = 4; REG Node = 'TENBASET_TxD:inst\|counter\[0\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.753 ns" { altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|counter[0] } "NODE_NAME" } } { "k20test.v" "" { Text "F:/NIOS2/k21test/k20test.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 24.15 % ) " "Info: Total cell delay = 0.666 ns ( 24.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.092 ns ( 75.85 % ) " "Info: Total interconnect delay = 2.092 ns ( 75.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.758 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|counter[0] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.758 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|counter[0] } { 0.000ns 1.005ns 1.087ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 source 2.758 ns - Shortest register " "Info: - Shortest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.758 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.005 ns) + CELL(0.000 ns) 1.005 ns altpll0:inst1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 113 " "Info: 2: + IC(1.005 ns) + CELL(0.000 ns) = 1.005 ns; Loc. = CLKCTRL_G3; Fanout = 113; COMB Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.005 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.087 ns) + CELL(0.666 ns) 2.758 ns TENBASET_TxD:inst\|counter\[0\] 3 REG LCFF_X42_Y13_N9 4 " "Info: 3: + IC(1.087 ns) + CELL(0.666 ns) = 2.758 ns; Loc. = LCFF_X42_Y13_N9; Fanout = 4; REG Node = 'TENBASET_TxD:inst\|counter\[0\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.753 ns" { altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|counter[0] } "NODE_NAME" } } { "k20test.v" "" { Text "F:/NIOS2/k21test/k20test.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 24.15 % ) " "Info: Total cell delay = 0.666 ns ( 24.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.092 ns ( 75.85 % ) " "Info: Total interconnect delay = 2.092 ns ( 75.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFl