k20test.tan.qmsg

只需要FPGA两个通用管脚

{ "Info" "ITDB_FULL_SLACK_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 memory lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|altsyncram_uqe2:altsyncram1\|q_a\[7\] register TENBASET_TxD:inst\|pkt_data\[7\] 5.503 ns " "Info: Slack time is 5.503 ns for clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" between source memory \"lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|altsyncram_uqe2:altsyncram1\|q_a\[7\]\" and destination register \"TENBASET_TxD:inst\|pkt_data\[7\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "6.729 ns + Largest memory register " "Info: + Largest memory to register requirement is 6.729 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "7.384 ns + " "Info: + Setup relationship between source and destination is 7.384 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 7.384 ns " "Info: + Latch edge is 7.384 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst1\|altpll:altpll_component\|_clk0 50.000 ns -2.616 ns  50 " "Info: Clock period of Destination clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is 50.000 ns with  offset of -2.616 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.435 ns + Largest " "Info: + Largest clock skew is -0.435 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 destination 2.749 ns + Shortest register " "Info: + Shortest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.749 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.005 ns) + CELL(0.000 ns) 1.005 ns altpll0:inst1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 113 " "Info: 2: + IC(1.005 ns) + CELL(0.000 ns) = 1.005 ns; Loc. = CLKCTRL_G3; Fanout = 113; COMB Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.005 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.078 ns) + CELL(0.666 ns) 2.749 ns TENBASET_TxD:inst\|pkt_data\[7\] 3 REG LCFF_X40_Y14_N1 1 " "Info: 3: + IC(1.078 ns) + CELL(0.666 ns) = 2.749 ns; Loc. = LCFF_X40_Y14_N1; Fanout = 1; REG Node = 'TENBASET_TxD:inst\|pkt_data\[7\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.744 ns" { altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|pkt_data[7] } "NODE_NAME" } } { "k20test.v" "" { Text "F:/NIOS2/k21test/k20test.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 24.23 % ) " "Info: Total cell delay = 0.666 ns ( 24.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.083 ns ( 75.77 % ) " "Info: Total interconnect delay = 2.083 ns ( 75.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.749 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|pkt_data[7] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.749 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|pkt_data[7] } { 0.000ns 1.005ns 1.078ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.184 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 3.184 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'clk'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "k20test.bdf" "" { Schematic "F:/NIOS2/k21test/k20test.bdf" { { 144 -216 -48 160 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.357 ns clk~clkctrl 2 COMB CLKCTRL_G2 15 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G2; Fanout = 15; COMB Node = 'clk~clkctrl'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.257 ns" { clk clk~clkctrl } "NODE_NAME" } } { "k20test.bdf" "" { Schematic "F:/NIOS2/k21test/k20test.bdf" { { 144 -216 -48 160 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.012 ns) + CELL(0.815 ns) 3.184 ns lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|altsyncram_uqe2:altsyncram1\|q_a\[7\] 3 MEM M4K_X41_Y14 1 " "Info: 3: + IC(1.012 ns) + CELL(0.815 ns) = 3.184 ns; Loc. = M4K_X41_Y14; Fanout = 1; MEM Node = 'lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|altsyncram_uqe2:altsyncram1\|q_a\[7\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.827 ns" { clk~clkctrl lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|q_a[7] } "NODE_NAME" } } { "db/altsyncram_uqe2.tdf" "" { Text "F:/NIOS2/k21test/db/altsyncram_uqe2.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.915 ns ( 60.14 % ) " "Info: Total cell delay = 1.915 ns ( 60.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.269 ns ( 39.86 % ) " "Info: Total interconnect delay = 1.269 ns ( 39.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.184 ns" { clk clk~clkctrl lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|q_a[7] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.184 ns" { clk clk~combout clk~clkctrl lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|q_a[7] } { 0.000ns 0.000ns 0.257ns 1.012ns } { 0.000ns 1.100ns 0.000ns 0.815ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.749 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|pkt_data[7] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.749 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|pkt_data[7] } { 0.000ns 1.005ns 1.078ns } { 0.000ns 0.000ns 0.666ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.184 ns" { clk clk~clkctrl lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|q_a[7] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.184 ns" { clk clk~combout clk~clkctrl lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|q_a[7] } { 0.000ns 0.000ns 0.257ns 1.012ns } { 0.000ns 1.100ns 0.000ns 0.815ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns - " "Info: - Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_uqe2.tdf" "" { Text "F:/NIOS2/k21test/db/altsyncram_uqe2.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns - " "Info: - Micro setup delay of destination is -0.040 ns" {  } { { "k20test.v" "" { Text "F:/NIOS2/k21test/k20test.v" 48 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.749 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|pkt_data[7] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.749 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|pkt_data[7] } { 0.000ns 1.005ns 1.078ns } { 0.000ns 0.000ns 0.666ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.184 ns" { clk clk~clkctrl lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|q_a[7] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.184 ns" { clk clk~combout clk~clkctrl lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|q_a[7] } { 0.000ns 0.000ns 0.257ns 1.012ns } { 0.000ns 1.100ns 0.000ns 0.815ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.226 ns - Longest memory register " "Info: - Longest memory to register delay is 1.226 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.109 ns) 0.109 ns lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|altsyncram_uqe2:altsyncram1\|q_a\[7\] 1 MEM M4K_X41_Y14 1 " "Info: 1: + IC(0.000 ns) + CELL(0.109 ns) = 0.109 ns; Loc. = M4K_X41_Y14; Fanout = 1; MEM Node = 'lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|altsyncram_uqe2:altsyncram1\|q_a\[7\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|q_a[7] } "NODE_NAME" } } { "db/altsyncram_uqe2.tdf" "" { Text "F:/NIOS2/k21test/db/altsyncram_uqe2.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.643 ns) + CELL(0.366 ns) 1.118 ns TENBASET_TxD:inst\|pkt_data~225 2 COMB LCCOMB_X40_Y14_N0 1 " "Info: 2: + IC(0.643 ns) + CELL(0.366 ns) = 1.118 ns; Loc. = LCCOMB_X40_Y14_N0; Fanout = 1; COMB Node = 'TENBASET_TxD:inst\|pkt_data~225'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.009 ns" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|q_a[7] TENBASET_TxD:inst|pkt_data~225 } "NODE_NAME" } } { "k20test.v" "" { Text "F:/NIOS2/k21test/k20test.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.226 ns TENBASET_TxD:inst\|pkt_data\[7\] 3 REG LCFF_X40_Y14_N1 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.226 ns; Loc. = LCFF_X40_Y14_N1; Fanout = 1; REG Node = 'TENBASET_TxD:inst\|pkt_data\[7\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { TENBASET_TxD:inst|pkt_data~225 TENBASET_TxD:inst|pkt_data[7] } "NODE_NAME" } } { "k20test.v" "" { Text "F:/NIOS2/k21test/k20test.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.583 ns ( 47.55 % ) " "Info: Total cell delay = 0.583 ns ( 47.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.643 ns ( 52.45 % ) " "Info: Total interconnect delay = 0.643 ns ( 52.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.226 ns" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|q_a[7] TENBASET_TxD:inst|pkt_data~225 TENBASET_TxD:inst|pkt_data[7] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "1.226 ns" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|q_a[7] TENBASET_TxD:inst|pkt_data~225 TENBASET_TxD:inst|pkt_data[7] } { 0.000ns 0.643ns 0.000ns } { 0.109ns 0.366ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.749 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|pkt_data[7] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.749 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|pkt_data[7] } { 0.000ns 1.005ns 1.078ns } { 0.000ns 0.000ns 0.666ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.184 ns" { clk clk~clkctrl lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|q_a[7] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.184 ns" { clk clk~combout clk~clkctrl lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|q_a[7] } { 0.000ns 0.000ns 0.257ns 1.012ns } { 0.000ns 1.100ns 0.000ns 0.815ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.226 ns" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|q_a[7] TENBASET_TxD:inst|pkt_data~225 TENBASET_TxD:inst|pkt_data[7] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "1.226 ns" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|q_a[7] TENBASET_TxD:inst|pkt_data~225 TENBASET_TxD:inst|pkt_data[7] } { 0.000ns 0.643ns 0.000ns } { 0.109ns 0.366ns 0.108ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clk register TENBASET_TxD:inst\|rdaddress\[4\] memory lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|altsyncram_uqe2:altsyncram1\|ram_block3a0~porta_address_reg4 804 ps " "Info: Slack time is 804 ps for clock \"clk\" between source register \"TENBASET_TxD:inst\|rdaddress\[4\]\" and destination memory \"lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|altsyncram_uqe2:altsyncram1\|ram_block3a0~porta_address_reg4\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "2.720 ns + Largest register memory " "Info: + Largest register to memory requirement is 2.720 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "2.616 ns + " "Info: + Setup relationship between source and destination is 2.616 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.000 ns " "Info: + Latch edge is 10.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 7.384 ns " "Info: - Launch edge is 7.384 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst1\|altpll:altpll_component\|_clk0 50.000 ns -2.616 ns  50 " "Info: Clock period of Source clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is 50.000 ns with  offset of -2.616 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.454 ns + Largest " "Info: + Largest clock skew is 0.454 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.204 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 3.204 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'clk'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "k20test.bdf" "" { Schematic "F:/NIOS2/k21test/k20test.bdf" { { 144 -216 -48 160 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.357 ns clk~clkctrl 2 COMB CLKCTRL_G2 15 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G2; Fanout = 15; COMB Node = 'clk~clkctrl'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.257 ns" { clk clk~clkctrl } "NODE_NAME" } } { "k20test.bdf" "" { Schematic "F:/NIOS2/k21test/k20test.bdf" { { 144 -216 -48 160 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.012 ns) + CELL(0.835 ns) 3.204 ns lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|altsyncram_uqe2:altsyncram1\|ram_block3a0~porta_address_reg4 3 MEM M4K_X41_Y14 8 " "Info: 3: + IC(1.012 ns) + CELL(0.835 ns) = 3.204 ns; Loc. = M4K_X41_Y14; Fanout = 8; MEM Node = 'lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|altsyncram_uqe2:altsyncram1\|ram_block3a0~porta_address_reg4'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.847 ns" { clk~clkctrl lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|ram_block3a0~porta_address_reg4 } "NODE_NAME" } } { "db/altsyncram_uqe2.tdf" "" { Text "F:/NIOS2/k21test/db/altsyncram_uqe2.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.935 ns ( 60.39 % ) " "Info: Total cell delay = 1.935 ns ( 60.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.269 ns ( 39.61 % ) " "Info: Total interconnect delay = 1.269 ns ( 39.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.204 ns" { clk clk~clkctrl lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|ram_block3a0~porta_address_reg4 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.204 ns" { clk clk~combout clk~clkctrl lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|ram_block3a0~porta_address_reg4 } { 0.000ns 0.000ns 0.257ns 1.012ns } { 0.000ns 1.100ns 0.000ns 0.835ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 source 2.750 ns - Longest register " "Info: - Longest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.750 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.005 ns) + CELL(0.000 ns) 1.005 ns altpll0:inst1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 113 " "Info: 2: + IC(1.005 ns) + CELL(0.000 ns) = 1.005 ns; Loc. = CLKCTRL_G3; Fanout = 113; COMB Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.005 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.079 ns) + CELL(0.666 ns) 2.750 ns TENBASET_TxD:inst\|rdaddress\[4\] 3 REG LCFF_X40_Y13_N15 4 " "Info: 3: + IC(1.079 ns) + CELL(0.666 ns) = 2.750 ns; Loc. = LCFF_X40_Y13_N15; Fanout = 4; REG Node = 'TENBASET_TxD:inst\|rdaddress\[4\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.745 ns" { altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|rdaddress[4] } "NODE_NAME" } } { "k20test.v" "" { Text "F:/NIOS2/k21test/k20test.v" 158 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 24.22 % ) " "Info: Total cell delay = 0.666 ns ( 24.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.084 ns ( 75.78 % ) " "Info: Total interconnect delay = 2.084 ns ( 75.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.750 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|rdaddress[4] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.750 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|rdaddress[4] } { 0.000ns 1.005ns 1.079ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.204 ns" { clk clk~clkctrl lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|ram_block3a0~porta_address_reg4 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.204 ns" { clk clk~combout clk~clkctrl lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|ram_block3a0~porta_address_reg4 } { 0.000ns 0.000ns 0.257ns 1.012ns } { 0.000ns 1.100ns 0.000ns 0.835ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.750 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|rdaddress[4] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.750 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|rdaddress[4] } { 0.000ns 1.005ns 1.079ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "k20test.v" "" { Text "F:/NIOS2/k21test/k20test.v" 158 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns - " "Info: - Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_uqe2.tdf" "" { Text "F:/NIOS2/k21test/db/altsyncram_uqe2.tdf" 48 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.204 ns" { clk clk~clkctrl lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|ram_block3a0~porta_address_reg4 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.204 ns" { clk clk~combout clk~clkctrl lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|ram_block3a0~porta_address_reg4 } { 0.000ns 0.000ns 0.257ns 1.012ns } { 0.000ns 1.100ns 0.000ns 0.835ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.750 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|rdaddress[4] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.750 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|rdaddress[4] } { 0.000ns 1.005ns 1.079ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.916 ns - Longest register memory " "Info: - Longest register to memory delay is 1.916 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns TENBASET_TxD:inst\|rdaddress\[4\] 1 REG LCFF_X40_Y13_N15 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X40_Y13_N15; Fanout = 4; REG Node = 'TENBASET_TxD:inst\|rdaddress\[4\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { TENBASET_TxD:inst|rdaddress[4] } "NODE_NAME" } } { "k20test.v" "" { Text "F:/NIOS2/k21test/k20test.v" 158 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.740 ns) + CELL(0.176 ns) 1.916 ns lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|altsyncram_uqe2:altsyncram1\|ram_block3a0~porta_address_reg4 2 MEM M4K_X41_Y14 8 " "Info: 2: + IC(1.740 ns) + CELL(0.176 ns) = 1.916 ns; Loc. = M4K_X41_Y14; Fanout = 8; MEM Node = 'lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|altsyncram_uqe2:altsyncram1\|ram_block3a0~porta_address_reg4'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.916 ns" { TENBASET_TxD:inst|rdaddress[4] lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|ram_block3a0~porta_address_reg4 } "NODE_NAME" } } { "db/altsyncram_uqe2.tdf" "" { Text "F:/NIOS2/k21test/db/altsyncram_uqe2.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.176 ns ( 9.19 % ) " "Info: Total cell delay = 0.176 ns ( 9.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.740 ns ( 90.81 % ) " "Info: Total interconnect delay = 1.740 ns ( 90.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.916 ns" { TENBASET_TxD:inst|rdaddress[4] lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|ram_block3a0~porta_address_reg4 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "1.916 ns" { TENBASET_TxD:inst|rdaddress[4] lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|ram_block3a0~porta_address_reg4 } { 0.000ns 1.740ns } { 0.000ns 0.176ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.204 ns" { clk clk~clkctrl lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|ram_block3a0~porta_address_reg4 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.204 ns" { clk clk~combout clk~clkctrl lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|ram_block3a0~porta_address_reg4 } { 0.000ns 0.000ns 0.257ns 1.012ns } { 0.000ns 1.100ns 0.000ns 0.835ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.750 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|rdaddress[4] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.750 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl TENBASET_TxD:inst|rdaddress[4] } { 0.000ns 1.005ns 1.079ns } { 0.000ns 0.000ns 0.666ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.916 ns" { TENBASET_TxD:inst|rdaddress[4] lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|ram_block3a0~porta_address_reg4 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "1.916 ns" { TENBASET_TxD:inst|rdaddress[4] lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|ram_block3a0~porta_address_reg4 } { 0.000ns 1.740ns } { 0.000ns 0.176ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}