k20test.hier_info

只需要FPGA两个通用管脚

|k20test
TDp <= TENBASET_TxD:inst.Ethernet_TDp
clk => altpll0:inst1.inclk0
clk => lpm_rom0:inst3.clock


|k20test|TENBASET_TxD:inst
clk20 => counter[22].CLK
clk20 => counter[21].CLK
clk20 => counter[20].CLK
clk20 => counter[19].CLK
clk20 => counter[18].CLK
clk20 => counter[17].CLK
clk20 => counter[16].CLK
clk20 => counter[15].CLK
clk20 => counter[14].CLK
clk20 => counter[13].CLK
clk20 => counter[12].CLK
clk20 => counter[11].CLK
clk20 => counter[10].CLK
clk20 => counter[9].CLK
clk20 => counter[8].CLK
clk20 => counter[7].CLK
clk20 => counter[6].CLK
clk20 => counter[5].CLK
clk20 => counter[4].CLK
clk20 => counter[3].CLK
clk20 => counter[2].CLK
clk20 => counter[1].CLK
clk20 => counter[0].CLK
clk20 => StartSending.CLK
clk20 => pkt_data[7].CLK
clk20 => pkt_data[6].CLK
clk20 => pkt_data[5].CLK
clk20 => pkt_data[4].CLK
clk20 => pkt_data[3].CLK
clk20 => pkt_data[2].CLK
clk20 => pkt_data[1].CLK
clk20 => pkt_data[0].CLK
clk20 => SendingPacket.CLK
clk20 => ShiftCount[3].CLK
clk20 => ShiftCount[2].CLK
clk20 => ShiftCount[1].CLK
clk20 => ShiftCount[0].CLK
clk20 => rdaddress[6]~reg0.CLK
clk20 => rdaddress[5]~reg0.CLK
clk20 => rdaddress[4]~reg0.CLK
clk20 => rdaddress[3]~reg0.CLK
clk20 => rdaddress[2]~reg0.CLK
clk20 => rdaddress[1]~reg0.CLK
clk20 => rdaddress[0]~reg0.CLK
clk20 => ShiftData[7].CLK
clk20 => ShiftData[6].CLK
clk20 => ShiftData[5].CLK
clk20 => ShiftData[4].CLK
clk20 => ShiftData[3].CLK
clk20 => ShiftData[2].CLK
clk20 => ShiftData[1].CLK
clk20 => ShiftData[0].CLK
clk20 => CRCflush.CLK
clk20 => CRCinit.CLK
clk20 => CRC[31].CLK
clk20 => CRC[30].CLK
clk20 => CRC[29].CLK
clk20 => CRC[28].CLK
clk20 => CRC[27].CLK
clk20 => CRC[26].CLK
clk20 => CRC[25].CLK
clk20 => CRC[24].CLK
clk20 => CRC[23].CLK
clk20 => CRC[22].CLK
clk20 => CRC[21].CLK
clk20 => CRC[20].CLK
clk20 => CRC[19].CLK
clk20 => CRC[18].CLK
clk20 => CRC[17].CLK
clk20 => CRC[16].CLK
clk20 => CRC[15].CLK
clk20 => CRC[14].CLK
clk20 => CRC[13].CLK
clk20 => CRC[12].CLK
clk20 => CRC[11].CLK
clk20 => CRC[10].CLK
clk20 => CRC[9].CLK
clk20 => CRC[8].CLK
clk20 => CRC[7].CLK
clk20 => CRC[6].CLK
clk20 => CRC[5].CLK
clk20 => CRC[4].CLK
clk20 => CRC[3].CLK
clk20 => CRC[2].CLK
clk20 => CRC[1].CLK
clk20 => CRC[0].CLK
clk20 => LinkPulseCount[17].CLK
clk20 => LinkPulseCount[16].CLK
clk20 => LinkPulseCount[15].CLK
clk20 => LinkPulseCount[14].CLK
clk20 => LinkPulseCount[13].CLK
clk20 => LinkPulseCount[12].CLK
clk20 => LinkPulseCount[11].CLK
clk20 => LinkPulseCount[10].CLK
clk20 => LinkPulseCount[9].CLK
clk20 => LinkPulseCount[8].CLK
clk20 => LinkPulseCount[7].CLK
clk20 => LinkPulseCount[6].CLK
clk20 => LinkPulseCount[5].CLK
clk20 => LinkPulseCount[4].CLK
clk20 => LinkPulseCount[3].CLK
clk20 => LinkPulseCount[2].CLK
clk20 => LinkPulseCount[1].CLK
clk20 => LinkPulseCount[0].CLK
clk20 => LinkPulse.CLK
clk20 => SendingPacketData.CLK
clk20 => idlecount[2].CLK
clk20 => idlecount[1].CLK
clk20 => idlecount[0].CLK
clk20 => qo.CLK
clk20 => qoe.CLK
clk20 => Ethernet_TDp~reg0.CLK
clk20 => Ethernet_TDm~reg0.CLK
clk20 => counter[23].CLK
Ethernet_TDp <= Ethernet_TDp~reg0.DB_MAX_OUTPUT_PORT_TYPE
Ethernet_TDm <= Ethernet_TDm~reg0.DB_MAX_OUTPUT_PORT_TYPE
inp[0] => pkt_data~7.DATAA
inp[1] => pkt_data~6.DATAA
inp[2] => pkt_data~5.DATAA
inp[3] => pkt_data~4.DATAA
inp[4] => pkt_data~3.DATAA
inp[5] => pkt_data~2.DATAA
inp[6] => pkt_data~1.DATAA
inp[7] => pkt_data~0.DATAA
rdaddress[0] <= rdaddress[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rdaddress[1] <= rdaddress[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rdaddress[2] <= rdaddress[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rdaddress[3] <= rdaddress[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rdaddress[4] <= rdaddress[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rdaddress[5] <= rdaddress[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rdaddress[6] <= rdaddress[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|k20test|altpll0:inst1
inclk0 => altpll:altpll_component.inclk[0]
c0 <= altpll:altpll_component.clk[0]


|k20test|altpll0:inst1|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= <UNC>
clk[2] <= <UNC>
clk[3] <= <UNC>
clk[4] <= <UNC>
clk[5] <= <UNC>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE


|k20test|lpm_rom0:inst3
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|k20test|lpm_rom0:inst3|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_q491:auto_generated.address_a[0]
address_a[1] => altsyncram_q491:auto_generated.address_a[1]
address_a[2] => altsyncram_q491:auto_generated.address_a[2]
address_a[3] => altsyncram_q491:auto_generated.address_a[3]
address_a[4] => altsyncram_q491:auto_generated.address_a[4]
address_a[5] => altsyncram_q491:auto_generated.address_a[5]
address_a[6] => altsyncram_q491:auto_generated.address_a[6]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_q491:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_q491:auto_generated.q_a[0]
q_a[1] <= altsyncram_q491:auto_generated.q_a[1]
q_a[2] <= altsyncram_q491:auto_generated.q_a[2]
q_a[3] <= altsyncram_q491:auto_generated.q_a[3]
q_a[4] <= altsyncram_q491:auto_generated.q_a[4]
q_a[5] <= altsyncram_q491:auto_generated.q_a[5]
q_a[6] <= altsyncram_q491:auto_generated.q_a[6]
q_a[7] <= altsyncram_q491:auto_generated.q_a[7]
q_b[0] <= <GND>


|k20test|lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated
address_a[0] => altsyncram_uqe2:altsyncram1.address_a[0]
address_a[1] => altsyncram_uqe2:altsyncram1.address_a[1]
address_a[2] => altsyncram_uqe2:altsyncram1.address_a[2]
address_a[3] => altsyncram_uqe2:altsyncram1.address_a[3]
address_a[4] => altsyncram_uqe2:altsyncram1.address_a[4]
address_a[5] => altsyncram_uqe2:altsyncram1.address_a[5]
address_a[6] => altsyncram_uqe2:altsyncram1.address_a[6]
clock0 => altsyncram_uqe2:altsyncram1.clock0
q_a[0] <= altsyncram_uqe2:altsyncram1.q_a[0]
q_a[1] <= altsyncram_uqe2:altsyncram1.q_a[1]
q_a[2] <= altsyncram_uqe2:altsyncram1.q_a[2]
q_a[3] <= altsyncram_uqe2:altsyncram1.q_a[3]
q_a[4] <= altsyncram_uqe2:altsyncram1.q_a[4]
q_a[5] <= altsyncram_uqe2:altsyncram1.q_a[5]
q_a[6] <= altsyncram_uqe2:altsyncram1.q_a[6]
q_a[7] <= altsyncram_uqe2:altsyncram1.q_a[7]


|k20test|lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4