k20test.fit.qmsg

只需要FPGA两个通用管脚

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "1 " "Warning: Found 1 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TDp 0 " "Info: Pin \"TDp\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|CLR_SIGNAL~clkctrl " "Info: Node sld_hub:sld_hub_inst\|CLR_SIGNAL~clkctrl uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] -- routed using non-global resources" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]" } } } } { "../../altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] -- routed using non-global resources" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\]" } } } } { "../../altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\] -- routed using non-global resources" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\]" } } } } { "../../altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[5\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[5\] -- routed using non-global resources" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5] } "NODE_NAME" } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[5\]" } } } } { "../../altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|bypass_reg_out " "Info: Port clear -- assigned as a global for destination node lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|bypass_reg_out -- routed using non-global resources" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out } "NODE_NAME" } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|bypass_reg_out" } } } } { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 183 -1 0 } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL~clkctrl } "NODE_NAME" } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|CLR_SIGNAL~clkctrl" } } } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL~clkctrl } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]~clkctrl " "Info: Node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]~clkctrl uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\] " "Info: Port clear -- assigned as a global for destination node lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\] -- routed using non-global resources" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0] } "NODE_NAME" } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]" } } } } { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[1\] " "Info: Port clear -- assigned as a global for destination node lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[1\] -- routed using non-global resources" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[1\]" } } } } { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[2\] " "Info: Port clear -- assigned as a global for destination node lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[2\] -- routed using non-global resources" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[2\]" } } } } { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[3\] " "Info: Port clear -- assigned as a global for destination node lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[3\] -- routed using non-global resources" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3] } "NODE_NAME" } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[3\]" } } } } { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[4\] " "Info: Port clear -- assigned as a global for destination node lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[4\] -- routed using non-global resources" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4] } "NODE_NAME" } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[4\]" } } } } { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[5\] " "Info: Port clear -- assigned as a global for destination node lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[5\] -- routed using non-global resources" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5] } "NODE_NAME" } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[5\]" } } } } { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[6\] " "Info: Port clear -- assigned as a global for destination node lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[6\] -- routed using non-global resources" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6] } "NODE_NAME" } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[6\]" } } } } { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0]~clkctrl } "NODE_NAME" } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]~clkctrl" } } } } { "../../altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0]~clkctrl } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 16 09:17:44 2008 " "Info: Processing ended: Sat Aug 16 09:17:44 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/NIOS2/k21test/k20test.fit.smsg " "Info: Generated suppressed messages file F:/NIOS2/k21test/k20test.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}