k20test.fit.qmsg

只需要FPGA两个通用管脚

{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.494 ns register memory " "Info: Estimated most critical path is register to memory delay of 1.494 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns TENBASET_TxD:inst\|rdaddress\[0\] 1 REG LAB_X40_Y13 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X40_Y13; Fanout = 12; REG Node = 'TENBASET_TxD:inst\|rdaddress\[0\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { TENBASET_TxD:inst|rdaddress[0] } "NODE_NAME" } } { "k20test.v" "" { Text "F:/NIOS2/k21test/k20test.v" 158 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.318 ns) + CELL(0.176 ns) 1.494 ns lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|altsyncram_uqe2:altsyncram1\|ram_block3a0~porta_address_reg0 2 MEM M4K_X41_Y14 1 " "Info: 2: + IC(1.318 ns) + CELL(0.176 ns) = 1.494 ns; Loc. = M4K_X41_Y14; Fanout = 1; MEM Node = 'lpm_rom0:inst3\|altsyncram:altsyncram_component\|altsyncram_q491:auto_generated\|altsyncram_uqe2:altsyncram1\|ram_block3a0~porta_address_reg0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.494 ns" { TENBASET_TxD:inst|rdaddress[0] lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_uqe2.tdf" "" { Text "F:/NIOS2/k21test/db/altsyncram_uqe2.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.176 ns ( 11.78 % ) " "Info: Total cell delay = 0.176 ns ( 11.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.318 ns ( 88.22 % ) " "Info: Total interconnect delay = 1.318 ns ( 88.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.494 ns" { TENBASET_TxD:inst|rdaddress[0] lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x38_y14 x50_y27 " "Info: The peak interconnect region extends from location x38_y14 to location x50_y27" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}