k20test.tan.summary

只需要FPGA两个通用管脚

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 0.708 ns
From           : altera_internal_jtag~TMSUTAP
To             : sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[0]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.317 ns
From           : TENBASET_TxD:inst|Ethernet_TDp
To             : TDp
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 3.016 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.077 ns
From           : altera_internal_jtag
To             : sld_hub:sld_hub_inst|HUB_BYPASS_REG
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : 0.804 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : TENBASET_TxD:inst|rdaddress[4]
To             : lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|ram_block3a0~porta_address_reg4
From Clock     : altpll0:inst1|altpll:altpll_component|_clk0
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'altpll0:inst1|altpll:altpll_component|_clk0'
Slack          : 5.503 ns
Required Time  : 20.00 MHz ( period = 50.000 ns )
Actual Time    : N/A
From           : lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|q_a[7]
To             : TENBASET_TxD:inst|pkt_data[7]
From Clock     : clk
To Clock       : altpll0:inst1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 85.22 MHz ( period = 11.734 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'altpll0:inst1|altpll:altpll_component|_clk0'
Slack          : 0.499 ns
Required Time  : 20.00 MHz ( period = 50.000 ns )
Actual Time    : N/A
From           : TENBASET_TxD:inst|counter[0]
To             : TENBASET_TxD:inst|counter[0]
From Clock     : altpll0:inst1|altpll:altpll_component|_clk0
To Clock       : altpll0:inst1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : 3.654 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|ram_block3a0~porta_address_reg6
To             : lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|q_a[7]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------