k20test.tan.rpt

只需要FPGA两个通用管脚

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+------------------------------------------------------------+----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+---------------------------------------------+--------------+
; Type                                                       ; Slack    ; Required Time                    ; Actual Time                      ; From                                                                                                                                      ; To                                                                                                                                        ; From Clock                                  ; To Clock                                    ; Failed Paths ;
+------------------------------------------------------------+----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+---------------------------------------------+--------------+
; Worst-case tsu                                             ; N/A      ; None                             ; 0.708 ns                         ; altera_internal_jtag~TMSUTAP                                                                                                              ; sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[0]                                                   ; --                                          ; altera_internal_jtag~TCKUTAP                ; 0            ;
; Worst-case tco                                             ; N/A      ; None                             ; 6.317 ns                         ; TENBASET_TxD:inst|Ethernet_TDp                                                                                                            ; TDp                                                                                                                                       ; clk                                         ; --                                          ; 0            ;
; Worst-case tpd                                             ; N/A      ; None                             ; 3.016 ns                         ; altera_internal_jtag~TDO                                                                                                                  ; altera_reserved_tdo                                                                                                                       ; --                                          ; --                                          ; 0            ;
; Worst-case th                                              ; N/A      ; None                             ; 2.077 ns                         ; altera_internal_jtag                                                                                                                      ; sld_hub:sld_hub_inst|HUB_BYPASS_REG                                                                                                       ; --                                          ; altera_internal_jtag~TCKUTAP                ; 0            ;
; Clock Setup: 'clk'                                         ; 0.804 ns ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; TENBASET_TxD:inst|rdaddress[4]                                                                                                            ; lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|ram_block3a0~porta_address_reg4 ; altpll0:inst1|altpll:altpll_component|_clk0 ; clk                                         ; 0            ;
; Clock Setup: 'altpll0:inst1|altpll:altpll_component|_clk0' ; 5.503 ns ; 20.00 MHz ( period = 50.000 ns ) ; N/A                              ; lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|q_a[7]                          ; TENBASET_TxD:inst|pkt_data[7]                                                                                                             ; clk                                         ; altpll0:inst1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'                ; N/A      ; None                             ; 85.22 MHz ( period = 11.734 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]                                                                                        ; sld_hub:sld_hub_inst|hub_tdo                                                                                                              ; altera_internal_jtag~TCKUTAP                ; altera_internal_jtag~TCKUTAP                ; 0            ;
; Clock Hold: 'altpll0:inst1|altpll:altpll_component|_clk0'  ; 0.499 ns ; 20.00 MHz ( period = 50.000 ns ) ; N/A                              ; TENBASET_TxD:inst|counter[0]                                                                                                              ; TENBASET_TxD:inst|counter[0]                                                                                                              ; altpll0:inst1|altpll:altpll_component|_clk0 ; altpll0:inst1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'clk'                                          ; 3.654 ns ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|ram_block3a0~porta_address_reg6 ; lpm_rom0:inst3|altsyncram:altsyncram_component|altsyncram_q491:auto_generated|altsyncram_uqe2:altsyncram1|q_a[7]                          ; clk                                         ; clk                                         ; 0            ;
; Total number of failed paths                               ;          ;                                  ;                                  ;                                                                                                                                           ;                                                                                                                                           ;                                             ;                                             ; 0            ;
+------------------------------------------------------------+----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+---------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C20F484C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+