spi_tb.vhd

关于SPI应用VHDL程序。供新手学习用。

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   23:06:04 07/24/2008
-- Design Name:   spi
-- Module Name:   spi_tb.vhd
-- Project Name:  spi
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: spi
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY spi_tb_vhd IS
END spi_tb_vhd;

ARCHITECTURE behavior OF spi_tb_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT spi
	PORT(
		reset : IN std_logic;
		sysclk : IN std_logic;
		cpu_wr : IN std_logic;
		cpu_rd : IN std_logic;
		cpu_cs : IN std_logic;
		cpu_addr : IN std_logic_vector(7 downto 0);
		data_in : IN std_logic_vector(7 downto 0);
		spi_i : IN std_logic;          
		data_out : OUT std_logic_vector(7 downto 0);
		buf_full : OUT std_logic;
		buf_emty : OUT std_logic;
		spi_o : OUT std_logic;
		sck_out : OUT std_logic;
		ss_n : OUT std_logic_vector(1 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL reset :  std_logic := '0';
	SIGNAL sysclk :  std_logic := '0';
	SIGNAL cpu_wr :  std_logic := '0';
	SIGNAL cpu_rd :  std_logic := '0';
	SIGNAL cpu_cs :  std_logic := '0';
	SIGNAL spi_i :  std_logic := '0';
	SIGNAL cpu_addr :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL data_in :  std_logic_vector(7 downto 0) := (others=>'0');

	--Outputs
	SIGNAL data_out :  std_logic_vector(7 downto 0);
	SIGNAL buf_full :  std_logic;
	SIGNAL buf_emty :  std_logic;
	SIGNAL spi_o :  std_logic;
	SIGNAL sck_out :  std_logic;
	SIGNAL ss_n :  std_logic_vector(1 downto 0);
	constant osc : time := 40 ns;

BEGIN
  sysclk <= not sysclk after osc/2;
	-- Instantiate the Unit Under Test (UUT)
	uut: spi PORT MAP(
		reset => reset,
		sysclk => sysclk,
		cpu_wr => cpu_wr,
		cpu_rd => cpu_rd,
		cpu_cs => cpu_cs,
		cpu_addr => cpu_addr,
		data_in => data_in,
		data_out => data_out,
		buf_full => buf_full,
		buf_emty => buf_emty,
		spi_o => spi_o,
		spi_i => spi_o,
		sck_out => sck_out,
		ss_n => ss_n
	);

	tb : PROCESS
	BEGIN

		reset <= '1';
		wait for 1000 ns;
      reset <= '0';
		cpu_cs <= '1';
		cpu_wr <= '1';
		cpu_addr <= x"00";
		data_in  <= x"02";
		wait for osc;
		cpu_addr <= x"01";
		data_in  <= x"56";
      wait for osc;
		cpu_cs <= '0';
		cpu_wr <= '0';
		wait for 8000 ns;
		cpu_cs <= '1';
		cpu_wr <= '1';
		cpu_addr <= x"01";
		data_in  <= x"78";
      wait for osc;
		cpu_wr <= '0';
		wait for osc;
	   cpu_rd <= '1';
		cpu_cs <= '1';
		cpu_addr <= x"00";
		wait for osc;
	   cpu_rd <= '0';
		cpu_cs <= '0';
		wait for osc;
		wait; -- will wait forever
	END PROCESS;

END;