songer.map.qmsg

乐曲硬件演奏电路设计的全部VHDL代码

{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Info: Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 20 " "Info: Parameter \"LPM_WIDTH\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "Songer.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/Songer.vhd" 38 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "Speakera:u3\|\\DelaySpkS:Count2 Speakera:u3\|SpkS " "Info: Duplicate register \"Speakera:u3\|\\DelaySpkS:Count2\" merged to single register \"Speakera:u3\|SpkS\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|otri\[3\] " "Warning: Converting TRI node \"NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|otri\[3\]\" that feeds logic to an OR gate" {  } { { "lpm_rom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_rom.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|otri\[0\] " "Warning: Converting TRI node \"NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|otri\[0\]\" that feeds logic to an OR gate" {  } { { "lpm_rom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_rom.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|otri\[1\] " "Warning: Converting TRI node \"NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|otri\[1\]\" that feeds logic to an OR gate" {  } { { "lpm_rom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_rom.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|otri\[2\] " "Warning: Converting TRI node \"NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|otri\[2\]\" that feeds logic to an OR gate" {  } { { "lpm_rom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_rom.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ToneTaba:u2\|HIGH " "Warning: Latch ToneTaba:u2\|HIGH has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[3\] " "Warning: Ports D and ENA on the latch are fed by the same signal NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[3\]" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 6 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ToneTaba:u2\|Tone\[10\] " "Warning: Latch ToneTaba:u2\|Tone\[10\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ToneTaba:u2\|Tone\[9\] " "Warning: Latch ToneTaba:u2\|Tone\[9\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ToneTaba:u2\|Tone\[8\] " "Warning: Latch ToneTaba:u2\|Tone\[8\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ToneTaba:u2\|Tone\[7\] " "Warning: Latch ToneTaba:u2\|Tone\[7\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ToneTaba:u2\|Tone\[6\] " "Warning: Latch ToneTaba:u2\|Tone\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ToneTaba:u2\|Tone\[5\] " "Warning: Latch ToneTaba:u2\|Tone\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ToneTaba:u2\|Tone\[4\] " "Warning: Latch ToneTaba:u2\|Tone\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ToneTaba:u2\|Tone\[3\] " "Warning: Latch ToneTaba:u2\|Tone\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ToneTaba:u2\|Tone\[2\] " "Warning: Latch ToneTaba:u2\|Tone\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ToneTaba:u2\|Tone\[1\] " "Warning: Latch ToneTaba:u2\|Tone\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ToneTaba:u2\|Tone\[0\] " "Warning: Latch ToneTaba:u2\|Tone\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[3\] " "Warning: Ports D and ENA on the latch are fed by the same signal NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[3\]" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "109 " "Info: Implemented 109 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "102 " "Info: Implemented 102 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "4 " "Info: Implemented 4 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 32 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 32 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 09 14:07:21 2007 " "Info: Processing ended: Fri Nov 09 14:07:21 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}