songer.map.qmsg

乐曲硬件演奏电路设计的全部VHDL代码

{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "HIGH ToneTaba.vhd(11) " "Warning (10631): VHDL Process Statement warning at ToneTaba.vhd(11): inferring latch(es) for signal or variable \"HIGH\", which holds its previous value in one or more paths through the process" {  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "HIGH ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"HIGH\"" {  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "CODE\[0\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"CODE\[0\]\"" {  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "CODE\[1\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"CODE\[1\]\"" {  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "CODE\[2\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"CODE\[2\]\"" {  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "CODE\[3\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"CODE\[3\]\"" {  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[0\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[0\]\"" {  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[1\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[1\]\"" {  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[2\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[2\]\"" {  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[3\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[3\]\"" {  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[4\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[4\]\"" {  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[5\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[5\]\"" {  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[6\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[6\]\"" {  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[7\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[7\]\"" {  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[8\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[8\]\"" {  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[9\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[9\]\"" {  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Tone\[10\] ToneTaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for \"Tone\[10\]\"" {  } { { "ToneTaba.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/ToneTaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Speakera Speakera:u3 " "Info: Elaborating entity \"Speakera\" for hierarchy \"Speakera:u3\"" {  } { { "Songer.vhd" "u3" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/Songer.vhd" 33 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "3 " "Info: Inferred 3 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Speakera:u3\|\\GenSpkS:Count11\[0\]~0 11 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=11) from the following logic: \"Speakera:u3\|\\GenSpkS:Count11\[0\]~0\"" {  } {  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "Speakera:u3\|\\DivideCLK:Count4\[0\]~0 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Speakera:u3\|\\DivideCLK:Count4\[0\]~0\"" {  } {  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "NoteTabs:u1\|Counter\[0\]~0 8 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: \"NoteTabs:u1\|Counter\[0\]~0\"" {  } { { "NoteTabs.vhd" "Counter\[0\]~0" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/NoteTabs.vhd" 18 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "Speakera:u3\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_0 " "Info: Elaborated megafunction instantiation \"Speakera:u3\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}