_primary.vhd

来自「MODELSIM的实验程序」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity SIM is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        counter_out     : out    vl_logic_vector(3 downto 0)
    );
end SIM;