_primary.vhd

来自「MODELSIM的实验程序」· VHDL 代码 · 共 9 行

library verilog;
use verilog.vl_types.all;
entity test_counter is
    generic(
        CLK_CYCLE       : integer := 20;
        CLK_HCYCLE      : integer := 10
    );
end test_counter;