p_3_8_decoder.v

3-8译码器地简单实现

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "07/12/2008 12:03:54"
                                                                        
// Verilog Self-Checking Test Bench (with test vectors) for design :    p_3_8_decoder
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module p_3_8_decoder_vlg_sample_tst(
	s1,
	sampler_tx
);
input [ 2 : 0 ] s1;
output sampler_tx;

reg sample ;

always @(s1)
                                                                                
begin                                         
 if ($time > 0)                               
 begin                                        
     if (sample === 1'bx)                     
	sample = 0;                           
     else                                     
        sample = ~sample;                     
 end                                          
end                                           

assign sampler_tx = sample;
endmodule

module p_3_8_decoder_vlg_check_tst (
	o1,sampler_rx
);
input [7:0] o1;
input sampler_rx;

reg [7:0] t__reg__o1_expected;

reg [7:0] t__reg__o1_prev;

reg [7:0] t__reg__o1_expected_prev;

reg [7:0] t__reg__last_o1_exp;

reg trigger;

integer i;
integer nummismatches;

reg [1:1] on_first_change ;


initial
begin
trigger = 0;
i = 0;
nummismatches = 0;
on_first_change = 1'b1;
end

// update real /o prevs

always @(trigger)
begin
	t__reg__o1_prev = o1;
end

// update expected /o prevs

always @(trigger)
begin
	t__reg__o1_expected_prev = t__reg__o1_expected;
end


// expected out[ 7 ]
initial
begin
	t__reg__o1_expected[7] = 1'bX;
end 
// expected out[ 6 ]
initial
begin
	t__reg__o1_expected[6] = 1'bX;
end 
// expected out[ 5 ]
initial
begin
	t__reg__o1_expected[5] = 1'bX;
end 
// expected out[ 4 ]
initial
begin
	t__reg__o1_expected[4] = 1'bX;
end 
// expected out[ 3 ]
initial
begin
	t__reg__o1_expected[3] = 1'bX;
end 
// expected out[ 2 ]
initial
begin
	t__reg__o1_expected[2] = 1'bX;
end 
// expected out[ 1 ]
initial
begin
	t__reg__o1_expected[1] = 1'bX;
end 
// expected out[ 0 ]
initial
begin
	t__reg__o1_expected[0] = 1'bX;
end 
// generate trigger
always @(t__reg__o1_expected or o1)
begin
	trigger <= ~trigger;
end

always @(posedge sampler_rx or negedge sampler_rx)
begin
`ifdef debug_tbench
	$display("Scanning pattern %d @time = %t",i,$realtime );
	i = i + 1;
	$display("| expected out = %b | ",t__reg__o1_expected_prev);
	$display("| real out = %b | ",t__reg__o1_prev);
`endif
	if (
		( t__reg__o1_expected_prev !== 8'bx ) && ( t__reg__o1_prev !== t__reg__o1_expected_prev )
		&& ((t__reg__o1_expected_prev !== t__reg__last_o1_exp) ||
			on_first_change[1])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port out :: @time = %t,Expected value = %b ; Real value = %b", $realtime, t__reg__o1_expected_prev, t__reg__o1_prev);
		nummismatches = nummismatches + 1;
		on_first_change[1] = 1'b0;
		t__reg__last_o1_exp = t__reg__o1_expected_prev;
	end

	trigger <= ~trigger;
end
initial 

begin 
$timeformat(-12,3," ps",6);
#1000000;
if (nummismatches > 0)
	$display ("%d mismatched vectors : Simulation failed !",nummismatches);
else
	$display ("Simulation passed !");
$stop;
end 
endmodule

module p_3_8_decoder_vlg_vec_tst();
// constants                                           
// general purpose registers                               
reg [2:0] t__reg__in;
// wires                                               
wire [2:0] t__wire__in;
wire [7:0] t__wire__out;

wire t__wire__sampler;                             

// assign statements (if any)                          
assign {t__wire__in} = {t__reg__in};
p_3_8_decoder tb (
// port map - connection between master ports and signals/registers   
	.in(t__wire__in),
	.out(t__wire__out)
);
// in[ 2 ]
initial
begin
	t__reg__in[2] = 1'b0;
	t__reg__in[2] = #20000 1'b1;
	t__reg__in[2] = #40000 1'b0;
	t__reg__in[2] = #50000 1'b1;
	t__reg__in[2] = #35000 1'b0;
end 
// in[ 1 ]
initial
begin
	t__reg__in[1] = 1'b0;
	t__reg__in[1] = #40000 1'b1;
	t__reg__in[1] = #160000 1'b0;
end 
// in[ 0 ]
initial
begin
	t__reg__in[0] = 1'b0;
	t__reg__in[0] = #5000 1'b1;
	t__reg__in[0] = #75000 1'b0;
	t__reg__in[0] = #80000 1'b1;
	t__reg__in[0] = #80000 1'b0;
end 

p_3_8_decoder_vlg_sample_tst tb_sample (
	.s1(t__wire__in),
	.sampler_tx(t__wire__sampler)
);

p_3_8_decoder_vlg_check_tst tb_out(
	.o1(t__wire__out),
	.sampler_rx(t__wire__sampler)
);
endmodule