decoder3to8.tan.rpt

3-8译码器地简单实现

Timing Analyzer report for decoder3to8
Tue Jul 22 08:12:13 2008
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                      ;
+------------------------------+-------+---------------+-------------+--------+---------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From   ; To      ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+--------+---------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 11.250 ns   ; din[0] ; dout[0] ;            ;          ; 0            ;
; Total number of failed paths ;       ;               ;             ;        ;         ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+--------+---------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+----------------------------------------------------------------+
; tpd                                                            ;
+-------+-------------------+-----------------+--------+---------+
; Slack ; Required P2P Time ; Actual P2P Time ; From   ; To      ;
+-------+-------------------+-----------------+--------+---------+
; N/A   ; None              ; 11.250 ns       ; din[0] ; dout[0] ;
; N/A   ; None              ; 11.236 ns       ; din[0] ; dout[3] ;
; N/A   ; None              ; 11.234 ns       ; din[0] ; dout[4] ;
; N/A   ; None              ; 11.233 ns       ; din[0] ; dout[5] ;
; N/A   ; None              ; 11.212 ns       ; din[0] ; dout[6] ;
; N/A   ; None              ; 10.965 ns       ; reset  ; dout[4] ;
; N/A   ; None              ; 10.962 ns       ; reset  ; dout[0] ;
; N/A   ; None              ; 10.951 ns       ; reset  ; dout[3] ;
; N/A   ; None              ; 10.947 ns       ; reset  ; dout[6] ;
; N/A   ; None              ; 10.944 ns       ; reset  ; dout[5] ;
; N/A   ; None              ; 10.919 ns       ; din[0] ; dout[7] ;
; N/A   ; None              ; 10.917 ns       ; din[0] ; dout[1] ;
; N/A   ; None              ; 10.907 ns       ; din[0] ; dout[2] ;
; N/A   ; None              ; 10.757 ns       ; din[1] ; dout[0] ;
; N/A   ; None              ; 10.753 ns       ; din[1] ; dout[4] ;
; N/A   ; None              ; 10.742 ns       ; din[1] ; dout[3] ;
; N/A   ; None              ; 10.739 ns       ; din[1] ; dout[5] ;
; N/A   ; None              ; 10.735 ns       ; din[1] ; dout[6] ;
; N/A   ; None              ; 10.641 ns       ; reset  ; dout[1] ;
; N/A   ; None              ; 10.639 ns       ; reset  ; dout[7] ;
; N/A   ; None              ; 10.634 ns       ; reset  ; dout[2] ;
; N/A   ; None              ; 10.427 ns       ; din[1] ; dout[1] ;
; N/A   ; None              ; 10.425 ns       ; din[1] ; dout[7] ;
; N/A   ; None              ; 10.422 ns       ; din[1] ; dout[2] ;
; N/A   ; None              ; 6.907 ns        ; din[2] ; dout[0] ;
; N/A   ; None              ; 6.900 ns        ; din[2] ; dout[4] ;
; N/A   ; None              ; 6.892 ns        ; din[2] ; dout[3] ;
; N/A   ; None              ; 6.890 ns        ; din[2] ; dout[5] ;
; N/A   ; None              ; 6.881 ns        ; din[2] ; dout[6] ;
; N/A   ; None              ; 6.576 ns        ; din[2] ; dout[7] ;
; N/A   ; None              ; 6.574 ns        ; din[2] ; dout[1] ;
; N/A   ; None              ; 6.568 ns        ; din[2] ; dout[2] ;
+-------+-------------------+-----------------+--------+---------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Jul 22 08:12:12 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off decoder3to8 -c decoder3to8 --timing_analysis_only
Info: Longest tpd from source pin "din[0]" to destination pin "dout[0]" is 11.250 ns
    Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_139; Fanout = 8; PIN Node = 'din[0]'
    Info: 2: + IC(5.503 ns) + CELL(0.590 ns) = 7.568 ns; Loc. = LC_X8_Y13_N6; Fanout = 1; COMB Node = 'dout~97'
    Info: 3: + IC(1.574 ns) + CELL(2.108 ns) = 11.250 ns; Loc. = PIN_129; Fanout = 0; PIN Node = 'dout[0]'
    Info: Total cell delay = 4.173 ns ( 37.09 % )
    Info: Total interconnect delay = 7.077 ns ( 62.91 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Jul 22 08:12:13 2008
    Info: Elapsed time: 00:00:01