baoshi.v

来自「基于vriloge的数字钟具有调时、分、秒和定时报警功能」· Verilog 代码 · 共 44 行

module baoshi(DATA,speak,ckosp,lope);
input[7:0]DATA;
wire[7:0]DATA;
input ckosp ;
output[3:0]lope;
output speak;
reg[3:0] lope;
reg speak;
reg[3:0]counter;
always @(posedge ckosp)begin
if(DATA==0)
      begin 
          speak=1;
          counter=counter+1;
      end
else       
      speak=0;
      
                      end
always @(counter)begin
case(counter)
0:lope=4'b0001;
1:lope=4'b0010;
2:lope=4'b0011;
3:lope=4'b0100;
4:lope=4'b0101;
5:lope=4'b0110;
6:lope=4'b0111;
7:lope=4'b1000;
8:lope=4'b1001;
9:lope=4'b1010;
default:lope=4'b1100;
endcase
                      end
endmodule