miniter.v

基于vriloge的数字钟具有调时、分、秒和定时报警功能

module miniter(ckmin,setminter,ckhour,A,B,Rest);
input ckmin,setminter,Rest;
output ckhour;
reg ckhour;
output[3:0]A,B;
reg[3:0]A,B;
wire cope;
assign cope=ckmin|setminter;
always @( negedge Rest or posedge cope  )begin
if(!Rest)begin A=0;B=0;end
else begin A=A+1;ckhour=0;end
if(A>9&&B>4)begin A=0;B=0;ckhour=1;end
else if(A>9)begin A=0;B=B+1;end
 end
 endmodule