second.v

基于vriloge的数字钟具有调时、分、秒和定时报警功能

module second(clk,Rest,A,B,ckmin);
output[3:0]A,B;
input clk,Rest;
output ckmin ;
reg[3:0]A,B;
reg ckmin;
always @(posedge clk )
     begin
         if(!Rest)
             begin 
             A=0;
             B=0;
             end
         else
            begin 
              A=A+1;
              ckmin=0;
          end

         if (A>9&&B>4) 
           begin 
                ckmin=1;
                 B=0;
                 A=0;
            end
         else if(A>9)
                 begin 
                    A=0;
                    B=B+1;
                  end
         
     end
endmodule