📄 clker.rpt
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09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhdl_ccd\clker.rpt
clker
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 18 clk
Device-Specific Information: d:\vhdl_ccd\clker.rpt
clker
** EQUATIONS **
clk : INPUT;
-- Node name is 'fccd'
-- Equation name is 'fccd', type is output
fccd = !fccdbuf;
-- Node name is ':11' = 'fccdbuf'
-- Equation name is 'fccdbuf', location is LC5_C11, type is buried.
fccdbuf = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = fccdbuf & step2
# fccdbuf & step3
# fccdbuf & !_LC1_C11
# !fccdbuf & _LC1_C11 & !step2 & !step3;
-- Node name is 'fm'
-- Equation name is 'fm', type is output
fm = !fmbuf;
-- Node name is ':6' = 'fmbuf'
-- Equation name is 'fmbuf', location is LC4_C19, type is buried.
fmbuf = DFFE(!fmbuf, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':22' = 'q0'
-- Equation name is 'q0', location is LC2_B24, type is buried.
q0 = DFFE(!q0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':21' = 'q1'
-- Equation name is 'q1', location is LC6_B24, type is buried.
q1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = q0 & !q1 & !q10
# _LC1_B24 & q0 & !q1
# !q0 & q1 & !q10
# _LC1_B24 & !q0 & q1;
-- Node name is ':20' = 'q2'
-- Equation name is 'q2', location is LC5_B24, type is buried.
q2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC4_B24 & !q0 & q2
# _LC4_B24 & !q1 & q2
# _LC4_B24 & q0 & q1 & !q2;
-- Node name is ':19' = 'q3'
-- Equation name is 'q3', location is LC8_B17, type is buried.
q3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !_LC3_B17 & _LC4_B24 & q3
# _LC3_B17 & _LC4_B24 & !q3;
-- Node name is ':18' = 'q4'
-- Equation name is 'q4', location is LC7_B17, type is buried.
q4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC4_B24 & !q3 & q4
# !_LC3_B17 & _LC4_B24 & q4
# _LC3_B17 & _LC4_B24 & q3 & !q4;
-- Node name is ':17' = 'q5'
-- Equation name is 'q5', location is LC6_B17, type is buried.
q5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC4_B24 & !q4 & q5
# _LC4_B24 & !_LC5_B17 & q5
# _LC4_B24 & _LC5_B17 & q4 & !q5;
-- Node name is ':16' = 'q6'
-- Equation name is 'q6', location is LC3_B22, type is buried.
q6 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !_LC4_B17 & _LC4_B24 & q6
# _LC4_B17 & _LC4_B24 & !q6;
-- Node name is ':15' = 'q7'
-- Equation name is 'q7', location is LC1_B22, type is buried.
q7 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = _LC4_B24 & !q6 & q7
# !_LC4_B17 & _LC4_B24 & q7
# _LC4_B17 & _LC4_B24 & q6 & !q7;
-- Node name is ':14' = 'q8'
-- Equation name is 'q8', location is LC8_B22, type is buried.
q8 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = !_LC4_B22 & _LC4_B24 & q8
# _LC4_B24 & !q7 & q8
# _LC4_B22 & _LC4_B24 & q7 & !q8;
-- Node name is ':13' = 'q9'
-- Equation name is 'q9', location is LC2_B22, type is buried.
q9 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = _LC4_B24 & !_LC6_B22 & q9
# _LC4_B24 & _LC6_B22 & !q9;
-- Node name is ':12' = 'q10'
-- Equation name is 'q10', location is LC5_B22, type is buried.
q10 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = _LC4_B24 & !q9 & q10
# _LC4_B24 & !_LC6_B22 & q10
# _LC4_B24 & _LC6_B22 & q9 & !q10;
-- Node name is 'sh'
-- Equation name is 'sh', type is output
sh = _LC7_B24;
-- Node name is ':10' = 'step0'
-- Equation name is 'step0', location is LC4_C11, type is buried.
step0 = DFFE(!step0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':9' = 'step1'
-- Equation name is 'step1', location is LC3_C11, type is buried.
step1 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = !_LC2_C11 & step0 & !step1
# !_LC2_C11 & !step0 & step1;
-- Node name is ':8' = 'step2'
-- Equation name is 'step2', location is LC6_C11, type is buried.
step2 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = !_LC1_C11 & !_LC2_C11 & step2
# _LC1_C11 & !_LC2_C11 & !step2;
-- Node name is ':7' = 'step3'
-- Equation name is 'step3', location is LC7_C11, type is buried.
step3 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = !_LC2_C11 & !step2 & step3
# !_LC1_C11 & !_LC2_C11 & step3
# _LC1_C11 & !_LC2_C11 & step2 & !step3;
-- Node name is '|LPM_ADD_SUB:123|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_C11', type is buried
_LC1_C11 = LCELL( _EQ015);
_EQ015 = step0 & step1;
-- Node name is '|LPM_ADD_SUB:415|addcore:adder|:91' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B17', type is buried
_LC3_B17 = LCELL( _EQ016);
_EQ016 = q0 & q1 & q2;
-- Node name is '|LPM_ADD_SUB:415|addcore:adder|:95' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B17', type is buried
_LC5_B17 = LCELL( _EQ017);
_EQ017 = _LC3_B17 & q3;
-- Node name is '|LPM_ADD_SUB:415|addcore:adder|:103' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B17', type is buried
_LC4_B17 = LCELL( _EQ018);
_EQ018 = _LC3_B17 & q3 & q4 & q5;
-- Node name is '|LPM_ADD_SUB:415|addcore:adder|:107' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B22', type is buried
_LC4_B22 = LCELL( _EQ019);
_EQ019 = _LC4_B17 & q6;
-- Node name is '|LPM_ADD_SUB:415|addcore:adder|:115' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B22', type is buried
_LC6_B22 = LCELL( _EQ020);
_EQ020 = _LC4_B17 & q6 & q7 & q8;
-- Node name is ':4'
-- Equation name is '_LC7_B24', type is buried
_LC7_B24 = DFFE( _EQ021, GLOBAL( clk), VCC, VCC, VCC);
_EQ021 = !_LC3_B24 & !q10
# !_LC1_B24 & _LC7_B24 & q10;
-- Node name is ':92'
-- Equation name is '_LC2_C11', type is buried
!_LC2_C11 = _LC2_C11~NOT;
_LC2_C11~NOT = LCELL( _EQ022);
_EQ022 = step2
# step3
# !_LC1_C11;
-- Node name is '~179~1'
-- Equation name is '~179~1', location is LC1_B24, type is buried.
-- synthesized logic cell
_LC1_B24 = LCELL( _EQ023);
_EQ023 = !q6
# !q0
# !q1
# _LC1_B17;
-- Node name is '~238~1'
-- Equation name is '~238~1', location is LC2_B17, type is buried.
-- synthesized logic cell
_LC2_B17 = LCELL( _EQ024);
_EQ024 = q4
# q5
# q8
# q7;
-- Node name is '~238~2'
-- Equation name is '~238~2', location is LC1_B17, type is buried.
-- synthesized logic cell
_LC1_B17 = LCELL( _EQ025);
_EQ025 = _LC2_B17
# q2
# q9
# q3;
-- Node name is '~238~3'
-- Equation name is '~238~3', location is LC3_B24, type is buried.
-- synthesized logic cell
_LC3_B24 = LCELL( _EQ026);
_EQ026 = q6
# _LC1_B17
# q0 & q1;
-- Node name is '~563~1'
-- Equation name is '~563~1', location is LC4_B24, type is buried.
-- synthesized logic cell
_LC4_B24 = LCELL( _EQ027);
_EQ027 = _LC1_B24 & q10
# _LC3_B24 & !q10
# _LC1_B24 & _LC3_B24;
Project Information d:\vhdl_ccd\clker.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,379K
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