clkdr.vhd

用VHDL语言实现的图像传感器TCD132D的时序驱动代码,时序精准!

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clker is
 port
 (
  clk:in std_logic;
  fm: buffer std_logic;
  fccd: buffer std_logic;
  sh: buffer std_logic
 );
end clker;
architecture one of clker is
 signal q:integer range 0 to 1092;
 signal step: std_logic_vector(3 downto 0);
 signal fmbuf:std_logic;
 signal fccdbuf:std_logic;
begin
 process(clk)
 begin
  if clk'event and clk='1' then
   fmbuf<=not fmbuf;
   if step="0011" then fccdbuf<= not fccdbuf;step<="0000";
   else step<=step+1;
   end if;

   if q=1091 then q<=0;
    else if q<3 then sh<='1';q<=q+1;
    else sh<='0';q<=q+1;
    end if;
   end if;
  end if;
 end process;
fm<=not fmbuf;
fccd<=not fccdbuf;
end;