pci.h

OpenSource GPS is software for x86 PCs that allows you to acquire, track and demodulate signals from

// nonstandard
//
// measured in 32-bit words
//
#define pci_get_threshold(h) pci_read_config_8(h,0x42)

// nonstandard
//
#define pci_set_threshold(h,v) pci_write_config_8(h,0x42,v)

#ifdef __cplusplus
}
#endif



#if _82437FX
// as far as I know, only defined on 82437FX
// System Controller
//
// it is recommended to use 3 or 5 PCI clocks for the
// CPU inactivity timer
//
struct PciControl
{
    Bit8 bus_concurrency_disable    : 1;
    Bit8 pci_streaming_disable      : 1;
    Bit8 cpu_to_pci_write_bursting_disable : 1;
    Bit8 peer_concurrency_enable    : 1;
    Bit8                            : 1;
    Bit8 cpu_inactivity_timer       : 3;        // actual value minus one, measured in PCI clocks
};
#else
#if _82439HX
// as far as I know, only defined on 82439HX
// System Controller
//
struct PciControl
{
    Bit8 global_txc_enable          : 1;
    Bit8                            : 1;        // reserved
    Bit8 serr_pound_output_type     : 1;        // 0=open drain compatible with PCI, 1=normal output driven high when negated
    Bit8 peer_concurrency_enable    : 1;
    Bit8 dual_processor_na_pound_enable : 1;    // 0=use 82437FX policies, 1=use policies for dual-procesor PCI 2.1
    Bit8 shutdown_to_port_92        : 1;        // 0=forward host shutdown cycle to PCI bus, 1=write 01h to port 92
    Bit8 ecc_test_enable            : 1;        // 0=normal mode, 1=test mode
    Bit8 dram_ecc_or_parity_select  : 1;        // 0=parity, 1=ECC (also adjusts DRAM timings)
};
#endif
#endif



#if _82437FX || _82439HX
// as far as I know, only defined on 82437FX
// and 82439HX System Controller
//
struct PciCacheControl
{
    Bit8 first_level_cache_enable   : 1;
    Bit8 secondary_cache_force_miss_or_invalidate : 1;
#if _82439HX
    Bit8 extended_cachability_enable : 1;       // 0=64MB 1=512MB (enables TIO[10:8] lines)
#else
    Bit8                            : 1;        // reserved (for guess who?)
#endif
    Bit8 na_pound_signal_disable    : 1;        // must be setup before either L1 or L2 cache is enabled... but what does NA# signal do?
    Bit8 static_ram_type            : 2;        // 00=pipe burst, 01=burst, 10=async, 11=512K dual bank pipe burst
    Bit8 secondary_cache_size       : 2;        // 00=not populated, 01=256K, 10=512K, 11=reserved
};

// Phil, for some reason this wouldn't work under Borland
/*
typedef enum PciCacheControlSramType
{
    pipelined_burst = 0,
    burst,                                      // reserved on 82439HX
    asynchronous,                               // reserved on 82439HX
    dual_512k_pipe_burst
};

typedef enum PciCacheControlSecondaryCacheSize
{
    not_populated = 0,
    has_256k,
    has_512k,
    reserved
};
*/
#endif



// as far as I know, only defined on 82371FB
// PCI ISA accelerator (PIIX)
//
struct PciSmiControl
{
    Bit8 smi_gate                   : 1;
    Bit8 stpclk_signal_enable       : 1;
    Bit8 stpclk_scaling_enable      : 1;
    Bit8 fastoff_timer_granularity  : 2;        // 00=minutes, 01=disabled, 10=PCICLK, 11=mS
    Bit8                            : 3;        // reserved
};

// Phil, for some reason this wouldn't work under Borland
/*
typedef enum PciSmiControlFastoffGranularity
{
    one_minute = 0,                 // actually 1.0 min @33 MHz PCICLK, 1.1 min @30 MHz, 1.32 min @25 MHz
    disabled,
    one_pci_clock,
    one_millisecond                 // actually 1.0 mS  @33 MHz PCICLK, 1.1 mS  @30 MHz, 1.32 mS  @25 MHz
};
*/


// as far as I know, only defined on 82371FB
// PCI ISA accelerator (PIIX)
//
struct PciSmiEnable
{
    Bit16 irq_1_smi_enable          : 1;        // keyboard
    Bit16 irq_3_smi_enable          : 1;        // COM1/COM3 or mouse
    Bit16 irq_4_smi_enable          : 1;        // COM2/COM4 or mouse
    Bit16 irq_8_smi_enable          : 1;        // realtime clock alarm
    Bit16 irq_12_smi_enable         : 1;        // PS/2 mouse
    Bit16 fastoff_timer_smi_enable  : 1;        // when it decrements to zero
    Bit16 extsmi_smi_enable         : 1;
    Bit16 apmc_write_enable         : 1;        // program's write to APM command register
    Bit16                           : 8;        // reserved
};



// as far as I know, only defined on 82371FB
// PCI ISA accelerator (PIIX)
//
// system events keep the system from powering down
// reloading the fast-off timer with its initial value
//
// break events can wake up a powered-down system by
// negating STPCLK#
//
// Phil, for some reason this wouldn't work under Borland
/*
struct PciSmiEventEnable
{
    Bit32 fastoff_irq_0_enable      : 1;        // system and break events
    Bit32 fastoff_irq_1_enable      : 1;        // system and break events
    Bit32                           : 1;
    Bit32 fastoff_irq_3_enable      : 1;        // system and break
    Bit32 fastoff_irq_4_enable      : 1;        // system and break
    Bit32 fastoff_irq_5_enable      : 1;        // system and break
    Bit32 fastoff_irq_6_enable      : 1;        // system and break
    Bit32 fastoff_irq_7_enable      : 1;        // system and break
    Bit32 fastoff_irq_8_enable      : 1;        // system and break
    Bit32 fastoff_irq_9_enable      : 1;        // system and break
    Bit32 fastoff_irq_10_enable     : 1;        // system and break
    Bit32 fastoff_irq_11_enable     : 1;        // system and break
    Bit32 fastoff_irq_12_enable     : 1;        // system and break
    Bit32 fastoff_irq_13_enable     : 1;        // system and break
    Bit32 fastoff_irq_14_enable     : 1;        // system and break
    Bit32 fastoff_irq_15_enable     : 1;        // system and break
    Bit32                           : 13;
    Bit32 fastoff_nmi_enable        : 1;        // system and break
    Bit32 intr_enable               : 1;        // break only
    Bit32 fastoff_smi_enable        : 1;        // system and break
};
*/


// as far as I know, only defined on 82371FB
// PCI ISA accelerator (PIIX)
//
// note that these are all edge sensitive, so if an
// SMI cause is still occurring when CPU writes zero
// to the corresponding bit in this register, the bit
// will not be set again by PIIX unless it goes away
// and comes back
//
struct PciSmiRequest
{
    Bit16 irq_1_caused_smi          : 1;
    Bit16 irq_3_caused_smi          : 1;
    Bit16 irq_4_caused_smi          : 1;
    Bit16 irq_8_caused_smi          : 1;
    Bit16 irq_12_caused_smi         : 1;
    Bit16 fastoff_timer_expired     : 1;        // but it reloaded and kept counting afterwards
    Bit16 extsmi_caused_smi         : 1;
    Bit16 apmc_write_caused_smi     : 1;
    Bit16                           : 8;
};



// as far as I know, only defined on 82437FX
// System Controller (TSC)
//
// note: software must ensure that smm_space_open
// and smm_space_closed are not both TRUE at the
// same time
//
struct PciSmiRamControl
{
    Bit8 smm_space_base_segment     : 3;        // must be 010 = A0000h to BFFFFh
    Bit8 sm_ram_enable              : 1;        // 128K bytes accessible when ADS# and SMIACT# asserted
    Bit8 smm_space_locked           : 1;        // smm_space_open and smm_space_closed become R/O; must reset to clear this bit
    Bit8 smm_space_closed           : 1;        // data passes through, code refs see SM RAM if SMIACT# asserted
    Bit8 smm_space_open             : 1;        // code & data see SM RAM regardles of SMIACT#
    Bit8                            : 1;        // reserved
};



// as far as I know, only defined on FORE PCA200E OC3c ATM NIC
//
struct PciMasterControl
{
    Bit8 disable_cache_line_reads   : 1;
    Bit8 disable_write_and_invals   : 1;
    Bit8 write_inval_needs_2_lines  : 1;
    Bit8 ignore_latency_timer       : 1;
    Bit8 enable_cont_request_mode   : 1;        // don't deassert REQ# if in and out BIFO's have threshold fullness
    Bit8 force_large_pci_bus_bursts : 1;        // (?input only) wait to assert REQ# until threshold input FIFO words available
    Bit8 byteswap_slave_ram_access  : 1;
    Bit8                            : 1;
};



// someday expand this interface so that the full
// 64 bytes of configuration registers defined in
// chapter 17 of PCI System Architecture, 3rd ed.
// including bit fields where necessary
//


#endif      // not included yet