pci.h

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#ifndef _PCI_H
#define _PCI_H



#include "types.h"

#ifdef __cplusplus
extern "C" {
#endif

#if __DPMI32__
#   define far
#   define _cdecl
#endif

int far _cdecl pci_is_bios_present( void );

#define PCI_CLOCK_RATE               33E6       // 33 MHz for 166 MHz CPU, 30 MHz for 120 MHz CPU
#define _82437FX                FALSE
#define _82439HX                TRUE





#define RETCODE_NO_MORE_PCI_DEVICES  0xFFFF

// structure of device ID (a.k.a handle)
//      bits 15:8       bus number
//            7:3       device number
//            2:0       function number (subdevice)
//
#define PCI_BUSSES_PER_MACHINE       16 
#define PCI_DEVICES_PER_BUS          32
#define PCI_FUNCTIONS_PER_DEVICE     8

Bit16 far _cdecl pci_get_device_handle(
    Bit16 device_id,
    Bit16 vendor_id,
    Bit16 index
);



// functions used by macros below
//

Bit32 far _cdecl pci_read_config_32( Bit16 device_id, Bit16 offset );
Bit16 far _cdecl pci_read_config_16( Bit16 device_id, Bit16 offset );
Bit8 far _cdecl pci_read_config_8( Bit16 device_id, Bit16 offset );
void far _cdecl pci_write_config_32( Bit16 device_id, Bit16 offset, Bit32 value );
void far _cdecl pci_write_config_16( Bit16 device_id, Bit16 offset, Bit16 value );
void far _cdecl pci_write_config_8( Bit16 device_id, Bit16 offset, Bit8 value );



// specific uses of PCI configuration space that work on all PCI devices
//

// mask off the control bits
//
// bit 0 = 0       use memory space
// bit 0 = 1       use I/O space (bits 3:1 reserved 0)
//
// bits 2:1 = 00   locate anywhere in 32-bit address space
// bits 2:1 = 01   locate below 1MB 
// bits 2:1 = 10   locate anywhere in 64-bit address space
// bits 2:1 = 11   reserved
//
// bit 3 = 0       not prefetchable
// bit 3 = 1       prefetchable
//
#define pci_get_base_address(h) (0xFFFFFFF0 & pci_read_config_32(h,0x10))
#define pci_get_base_address_n(h,i) (0xFFFFFFF0 & pci_read_config_32(h,0x10 + 4*(i)))

#define pci_get_irq_level(h) pci_read_config_8(h,0x3C)

#define pci_get_status(h) pci_read_config_16(h,0x06)

#define pci_get_command(h) pci_read_config_16(h,0x04)
#define pci_set_command(h,v) pci_write_config_16(h,0x04,v)

#define pci_get_revision(h) pci_read_config_8(h,0x08)

// wants to be an even multiple of 8; rounds down
//
#define pci_get_master_latency_timer(h) pci_read_config_8(h,0x0D)
#define pci_set_master_latency_timer(h,v) pci_write_config_8(h,0x0D,v)

// is read-only, so set does not work
//
// measured in .25 uS
//
#define pci_get_max_latency(h) pci_read_config_8(h,0x3F)
#define pci_set_max_latency(h,v) pci_write_config_8(h,0x3F,v)

// is read-only, so set doesn't work
//
// measured in .25 uS
//
#define pci_get_min_grant(h) pci_read_config_8(h,0x3E)
#define pci_set_min_grant(h,v) pci_write_config_8(h,0x3E,v)

#define pci_get_cache_line_size(h) pci_read_config_8(h,0x0C)
#define pci_set_cache_line_size(h,v) pci_write_config_8(h,0x0C,v)

// assumes little-endian bit ordering,
// and structure packing
//
struct PciCommand
{
    Bit16 input_output_space_enable : 1;
    Bit16 memory_space_enable       : 1;
    Bit16 bus_master_enable         : 1;
    Bit16 special_cycle_mon_enable  : 1;
    Bit16 mem_write_inval_enable    : 1;
    Bit16 vga_palette_snoop_enable  : 1;
    Bit16 parity_error_response     : 1;
    Bit16 stepping_enable           : 1;
    Bit16 system_error_response     : 1;
    Bit16 fast_back_to_back_enable  : 1;
    Bit16                           : 6;
};

struct PciStatus
{
    Bit16                           : 5;
    Bit16 is_66_mhz_capable         : 1;
    Bit16 user_def_feature_support  : 1;
    Bit16 fast_back_to_back_capable : 1;
    Bit16 signaled_parity_error     : 1;
    Bit16 devsel_timing             : 2;        // 00=fast 01=medium 10=slow 11=reserved
    Bit16 signaled_target_abort     : 1;
    Bit16 received_target_abort     : 1;
    Bit16 received_master_abort     : 1;
    Bit16 signaled_system_error     : 1;
    Bit16 detected_parity_error     : 1;
};



// stuff that is specific to motherboard chipsets
//

// how many PCI wait-states will add during the burst portion
// of a PCI master read or write cycle targeted (I think
// that means host memory)
//
// only defined for 82437VX
//
// 000 = 2 cycles
// 001 = 4 cycles
// 010 = 6 cycles
// 011 = 8 cycles (default, matches PCI 2.0)
// 1xx = reserved
//
#define pci_get_trdy_timer(h) pci_read_config_8(h,0x69)
#define pci_set_trdy_timer(h,v) pci_write_config_8(h,0x69,v)

// how long will a PCI master be allowed to retain ownership
// of the bus (from initial assertion of grant) (minimum)
//
// allows a PCI device to do multiple transactions by keeping
// its request asserted
//
// only defined for 82437VX and 82439HX
//
// measured in multiples of 4 PCI clock cycles
// (bottom 2 bits are forced to zeroes)
//
#define pci_get_multi_transaction_timer(h) pci_read_config_8(h,0x70)
#define pci_set_multi_transaction_timer(h,v) pci_write_config_8(h,0x70,v)

// only applies to 82437FX and 82439HX PCI/host bridge chips
//
// note that bit mapping is different on the 2 chips (see below)
//
#define pci_get_control(h) pci_read_config_8(h,0x50)
#define pci_set_control(h,v) pci_write_config_8(h,0x50,v)

// only applies to 82437FX and 82439HX PCI/host bridge chips
//
#define pci_get_cache_control(h) pci_read_config_8(h,0x52)
#define pci_set_cache_control(h,v) pci_write_config_8(h,0x52,v)

// only applies to 82371FB and 82371SB PCI/ISA accelerator (PIIX and PIIX3) chips
//
#define pci_get_smi_control(h) pci_read_config_8(h,0xA0)
#define pci_set_smi_control(h,v) pci_write_config_8(h,0xA0,v)

// only applies to 82371FB and 82371SB PCI/ISA accelerator (PIIX and PIIX3) chips
//
#define pci_get_smi_enable(h) pci_read_config_16(h,0xA2)
#define pci_set_smi_enable(h,v) pci_write_config_16(h,0xA2,v)

// only applies to 82371FB and 82371SB PCI/ISA accelerator (PIIX and PIIX3) chips
//
#define pci_get_smi_event_enable(h) pci_read_config_32(h,0xA4)
#define pci_set_smi_event_enable(h,v) pci_write_config_32(h,0xA4,v)

// only applies to 82371FB and 82371SB PCI/ISA accelerator (PIIX and PIIX3) chips
//
// has actual value minus 1
//
#define pci_get_smi_fastoff_timer(h) pci_read_config_8(h,0xA8)
#define pci_set_smi_fastoff_timer(h,v) pci_write_config_8(h,0xA8,v)

// only applies to 82371FB and 82371SB PCI/ISA accelerator (PIIX and PIIX3) chips
//
#define pci_get_smi_request(h) pci_read_config_16(h,0xAA)
#define pci_set_smi_request(h,v) pci_write_config_16(h,0xAA,v)

// only applies to 82437FX and 82439HX PCI/host bridge chips
//
#define pci_get_smi_ram_control(h) pci_read_config_8(h,0x72)
#define pci_set_smi_ram_control(h,v) pci_write_config_8(h,0x72,v)

// only applies to 82371FB and 82371SB PCI/ISA accelerator (PIIX and PIIX3) chips
//
#define pci_get_ide_timing_n(h,secondary_ch) pci_read_config_16(h,0x40+2*secondary_ch)
#define pci_set_ide_timing_n(h,secondary_ch,v) pci_write_config_16(h,0x40+2*secondary_ch,v)

// only applies to 82371FB and 82371SB PCI/ISA accelerator (PIIX and PIIX3) chips
//
#define pci_get_slave_ide_timing_n(h) pci_read_config_16(h,0x44)
#define pci_set_slave_ide_timing_n(h,v) pci_write_config_16(h,0x44,v)


//
// measured in cycles
//
#define pci_get_max_slave_latency(h) pci_read_config_8(h,0x40)
#define pci_set_max_slave_latency(h,v) pci_write_config_8(h,0x40,v)

// nonstandard
//
#define pci_get_master_control(h) pci_read_config_8(h,0x41)

// nonstandard
//
#define pci_set_master_control(h,v) pci_write_config_8(h,0x41,v)