dds.hier_info

实现dds功能

din[31] => dout[31]~reg0.DATAIN
dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[8] <= dout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[9] <= dout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[10] <= dout[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[11] <= dout[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[12] <= dout[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[13] <= dout[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[14] <= dout[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[15] <= dout[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[16] <= dout[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[17] <= dout[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[18] <= dout[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[19] <= dout[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[20] <= dout[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[21] <= dout[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[22] <= dout[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[23] <= dout[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[24] <= dout[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[25] <= dout[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[26] <= dout[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[27] <= dout[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[28] <= dout[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[29] <= dout[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[30] <= dout[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[31] <= dout[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|dds|adder32b:inst
A[0] => Add0.IN32
A[1] => Add0.IN31
A[2] => Add0.IN30
A[3] => Add0.IN29
A[4] => Add0.IN28
A[5] => Add0.IN27
A[6] => Add0.IN26
A[7] => Add0.IN25
A[8] => Add0.IN24
A[9] => Add0.IN23
A[10] => Add0.IN22
A[11] => Add0.IN21
A[12] => Add0.IN20
A[13] => Add0.IN19
A[14] => Add0.IN18
A[15] => Add0.IN17
A[16] => Add0.IN16
A[17] => Add0.IN15
A[18] => Add0.IN14
A[19] => Add0.IN13
A[20] => Add0.IN12
A[21] => Add0.IN11
A[22] => Add0.IN10
A[23] => Add0.IN9
A[24] => Add0.IN8
A[25] => Add0.IN7
A[26] => Add0.IN6
A[27] => Add0.IN5
A[28] => Add0.IN4
A[29] => Add0.IN3
A[30] => Add0.IN2
A[31] => Add0.IN1
B[0] => Add0.IN64
B[1] => Add0.IN63
B[2] => Add0.IN62
B[3] => Add0.IN61
B[4] => Add0.IN60
B[5] => Add0.IN59
B[6] => Add0.IN58
B[7] => Add0.IN57
B[8] => Add0.IN56
B[9] => Add0.IN55
B[10] => Add0.IN54
B[11] => Add0.IN53
B[12] => Add0.IN52
B[13] => Add0.IN51
B[14] => Add0.IN50
B[15] => Add0.IN49
B[16] => Add0.IN48
B[17] => Add0.IN47
B[18] => Add0.IN46
B[19] => Add0.IN45
B[20] => Add0.IN44
B[21] => Add0.IN43
B[22] => Add0.IN42
B[23] => Add0.IN41
B[24] => Add0.IN40
B[25] => Add0.IN39
B[26] => Add0.IN38
B[27] => Add0.IN37
B[28] => Add0.IN36
B[29] => Add0.IN35
B[30] => Add0.IN34
B[31] => Add0.IN33
S[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[10] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[11] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[12] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[13] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[14] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[15] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[16] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[17] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[18] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[19] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[20] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[21] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[22] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[23] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[24] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[25] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[26] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[27] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[28] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[29] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[30] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[31] <= Add0.DB_MAX_OUTPUT_PORT_TYPE


|dds|date_rom:inst10
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
inclock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|dds|date_rom:inst10|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_tr51:auto_generated.address_a[0]
address_a[1] => altsyncram_tr51:auto_generated.address_a[1]
address_a[2] => altsyncram_tr51:auto_generated.address_a[2]
address_a[3] => altsyncram_tr51:auto_generated.address_a[3]
address_a[4] => altsyncram_tr51:auto_generated.address_a[4]
address_a[5] => altsyncram_tr51:auto_generated.address_a[5]
address_a[6] => altsyncram_tr51:auto_generated.address_a[6]
address_a[7] => altsyncram_tr51:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_tr51:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_tr51:auto_generated.q_a[0]
q_a[1] <= altsyncram_tr51:auto_generated.q_a[1]
q_a[2] <= altsyncram_tr51:auto_generated.q_a[2]
q_a[3] <= altsyncram_tr51:auto_generated.q_a[3]
q_a[4] <= altsyncram_tr51:auto_generated.q_a[4]
q_a[5] <= altsyncram_tr51:auto_generated.q_a[5]
q_a[6] <= altsyncram_tr51:auto_generated.q_a[6]
q_a[7] <= altsyncram_tr51:auto_generated.q_a[7]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|dds|date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated
address_a[0] => altsyncram_aa72:altsyncram1.address_a[0]
address_a[1] => altsyncram_aa72:altsyncram1.address_a[1]
address_a[2] => altsyncram_aa72:altsyncram1.address_a[2]
address_a[3] => altsyncram_aa72:altsyncram1.address_a[3]
address_a[4] => altsyncram_aa72:altsyncram1.address_a[4]
address_a[5] => altsyncram_aa72:altsyncram1.address_a[5]
address_a[6] => altsyncram_aa72:altsyncram1.address_a[6]
address_a[7] => altsyncram_aa72:altsyncram1.address_a[7]
clock0 => altsyncram_aa72:altsyncram1.clock0
q_a[0] <= altsyncram_aa72:altsyncram1.q_a[0]
q_a[1] <= altsyncram_aa72:altsyncram1.q_a[1]
q_a[2] <= altsyncram_aa72:altsyncram1.q_a[2]
q_a[3] <= altsyncram_aa72:altsyncram1.q_a[3]
q_a[4] <= altsyncram_aa72:altsyncram1.q_a[4]
q_a[5] <= altsyncram_aa72:altsyncram1.q_a[5]
q_a[6] <= altsyncram_aa72:altsyncram1.q_a[6]
q_a[7] <= altsyncram_aa72:altsyncram1.q_a[7]


|dds|date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[5] => ram_block3a4.PORTAADDR5
address_a[5] => ram_block3a5.PORTAADDR5
address_a[5] => ram_block3a6.PORTAADDR5
address_a[5] => ram_block3a7.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[6] => ram_block3a4.PORTAADDR6
address_a[6] => ram_block3a5.PORTAADDR6
address_a[6] => ram_block3a6.PORTAADDR6
address_a[6] => ram_block3a7.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_a[7] => ram_block3a4.PORTAADDR7
address_a[7] => ram_block3a5.PORTAADDR7
address_a[7] => ram_block3a6.PORTAADDR7
address_a[7] => ram_block3a7.PORTAADDR7
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.PORTBADDR
address_b[0] => ram_block3a7.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[1] => ram_block3a4.PORTBADDR1
address_b[1] => ram_block3a5.PORTBADDR1
address_b[1] => ram_block3a6.PORTBADDR1
address_b[1] => ram_block3a7.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[2] => ram_block3a4.PORTBADDR2
address_b[2] => ram_block3a5.PORTBADDR2
address_b[2] => ram_block3a6.PORTBADDR2
address_b[2] => ram_block3a7.PORTBADDR2
address_b[3] => ram_block3a0.PORTBADDR3
address_b[3] => ram_block3a1.PORTBADDR3
address_b[3] => ram_block3a2.PORTBADDR3
address_b[3] => ram_block3a3.PORTBADDR3
address_b[3] => ram_block3a4.PORTBADDR3
address_b[3] => ram_block3a5.PORTBADDR3
address_b[3] => ram_block3a6.PORTBADDR3
address_b[3] => ram_block3a7.PORTBADDR3
address_b[4] => ram_block3a0.PORTBADDR4
address_b[4] => ram_block3a1.PORTBADDR4
address_b[4] => ram_block3a2.PORTBADDR4
address_b[4] => ram_block3a3.PORTBADDR4
address_b[4] => ram_block3a4.PORTBADDR4
address_b[4] => ram_block3a5.PORTBADDR4
address_b[4] => ram_block3a6.PORTBADDR4
address_b[4] => ram_block3a7.PORTBADDR4
address_b[5] => ram_block3a0.PORTBADDR5
address_b[5] => ram_block3a1.PORTBADDR5
address_b[5] => ram_block3a2.PORTBADDR5
address_b[5] => ram_block3a3.PORTBADDR5
address_b[5] => ram_block3a4.PORTBADDR5
address_b[5] => ram_block3a5.PORTBADDR5
address_b[5] => ram_block3a6.PORTBADDR5
address_b[5] => ram_block3a7.PORTBADDR5
address_b[6] => ram_block3a0.PORTBADDR6
address_b[6] => ram_block3a1.PORTBADDR6
address_b[6] => ram_block3a2.PORTBADDR6
address_b[6] => ram_block3a3.PORTBADDR6
address_b[6] => ram_block3a4.PORTBADDR6
address_b[6] => ram_block3a5.PORTBADDR6
address_b[6] => ram_block3a6.PORTBADDR6
address_b[6] => ram_block3a7.PORTBADDR6
address_b[7] => ram_block3a0.PORTBADDR7
address_b[7] => ram_block3a1.PORTBADDR7
address_b[7] => ram_block3a2.PORTBADDR7
address_b[7] => ram_block3a3.PORTBADDR7
address_b[7] => ram_block3a4.PORTBADDR7
address_b[7] => ram_block3a5.PORTBADDR7
address_b[7] => ram_block3a6.PORTBADDR7
address_b[7] => ram_block3a7.PORTBADDR7
clock0 => ram_block3a0.CLK0