dds.hier_info

实现dds功能

|dds
dac_clk <= pllu:inst3.c0
clk => pllu:inst3.inclk0
clk => fword:inst9.clk_48Mhz
clk => pword:inst11.clk_48Mhz
code[0] <= fword:inst9.code[0]
code[1] <= fword:inst9.code[1]
code[2] <= fword:inst9.code[2]
code[3] <= fword:inst9.code[3]
code[4] <= fword:inst9.code[4]
code[5] <= fword:inst9.code[5]
code[6] <= fword:inst9.code[6]
code[7] <= fword:inst9.code[7]
d => fword:inst9.d
d => pword:inst11.d
ps2_clk => fword:inst9.ps2_clk
ps2_clk => pword:inst11.ps2_clk
ps2_dat => fword:inst9.ps2_dat
ps2_dat => pword:inst11.ps2_dat
dac1[0] <= date_rom:inst2.q[0]
dac1[1] <= date_rom:inst2.q[1]
dac1[2] <= date_rom:inst2.q[2]
dac1[3] <= date_rom:inst2.q[3]
dac1[4] <= date_rom:inst2.q[4]
dac1[5] <= date_rom:inst2.q[5]
dac1[6] <= date_rom:inst2.q[6]
dac1[7] <= date_rom:inst2.q[7]
dac2[0] <= date_rom:inst10.q[0]
dac2[1] <= date_rom:inst10.q[1]
dac2[2] <= date_rom:inst10.q[2]
dac2[3] <= date_rom:inst10.q[3]
dac2[4] <= date_rom:inst10.q[4]
dac2[5] <= date_rom:inst10.q[5]
dac2[6] <= date_rom:inst10.q[6]
dac2[7] <= date_rom:inst10.q[7]
dip => ~NO_FANOUT~
pdip[0] => ~NO_FANOUT~
pdip[1] => ~NO_FANOUT~
pdip[2] => ~NO_FANOUT~
pdip[3] => ~NO_FANOUT~


|dds|pllu:inst3
areset => altpll:altpll_component.areset
inclk0 => altpll:altpll_component.inclk[0]
c0 <= altpll:altpll_component.clk[0]
locked <= altpll:altpll_component.locked


|dds|pllu:inst3|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => pll.ARESET
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <= <GND>
clk[0] <= clk[0]~0.DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= <GND>
clk[2] <= <GND>
clk[3] <= <GND>
clk[4] <= <GND>
clk[5] <= <GND>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= pll.LOCKED
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>


|dds|fword:inst9
fw[0] <= <GND>
fw[1] <= <GND>
fw[2] <= <GND>
fw[3] <= <GND>
fw[4] <= fdip[0].DB_MAX_OUTPUT_PORT_TYPE
fw[5] <= fdip[1].DB_MAX_OUTPUT_PORT_TYPE
fw[6] <= fdip[2].DB_MAX_OUTPUT_PORT_TYPE
fw[7] <= fdip[3].DB_MAX_OUTPUT_PORT_TYPE
clk_48Mhz => clkcnt2[9].CLK
clk_48Mhz => clkcnt2[8].CLK
clk_48Mhz => clkcnt2[7].CLK
clk_48Mhz => clkcnt2[6].CLK
clk_48Mhz => clkcnt2[5].CLK
clk_48Mhz => clkcnt2[4].CLK
clk_48Mhz => clkcnt2[3].CLK
clk_48Mhz => clkcnt2[2].CLK
clk_48Mhz => clkcnt2[1].CLK
clk_48Mhz => clkcnt2[0].CLK
d => process0~9.IN0
d => process0~8.IN0
d => process0~7.IN0
d => process0~6.IN0
d => process0~5.IN0
d => process0~4.IN0
d => process0~3.IN0
d => process0~2.IN0
d => process0~1.IN0
d => process0~0.IN0
ps2_clk => old_clk.DATAIN
ps2_clk => process2~0.IN1
ps2_dat => check~0.IN1
ps2_dat => dat[10].DATAIN
code[0] <= code[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
code[1] <= code[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
code[2] <= code[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
code[3] <= code[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
code[4] <= code[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
code[5] <= code[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
code[6] <= code[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
code[7] <= code[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|dds|date_rom:inst2
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
inclock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|dds|date_rom:inst2|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_tr51:auto_generated.address_a[0]
address_a[1] => altsyncram_tr51:auto_generated.address_a[1]
address_a[2] => altsyncram_tr51:auto_generated.address_a[2]
address_a[3] => altsyncram_tr51:auto_generated.address_a[3]
address_a[4] => altsyncram_tr51:auto_generated.address_a[4]
address_a[5] => altsyncram_tr51:auto_generated.address_a[5]
address_a[6] => altsyncram_tr51:auto_generated.address_a[6]
address_a[7] => altsyncram_tr51:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_tr51:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_tr51:auto_generated.q_a[0]
q_a[1] <= altsyncram_tr51:auto_generated.q_a[1]
q_a[2] <= altsyncram_tr51:auto_generated.q_a[2]
q_a[3] <= altsyncram_tr51:auto_generated.q_a[3]
q_a[4] <= altsyncram_tr51:auto_generated.q_a[4]
q_a[5] <= altsyncram_tr51:auto_generated.q_a[5]
q_a[6] <= altsyncram_tr51:auto_generated.q_a[6]
q_a[7] <= altsyncram_tr51:auto_generated.q_a[7]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|dds|date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated
address_a[0] => altsyncram_aa72:altsyncram1.address_a[0]
address_a[1] => altsyncram_aa72:altsyncram1.address_a[1]
address_a[2] => altsyncram_aa72:altsyncram1.address_a[2]
address_a[3] => altsyncram_aa72:altsyncram1.address_a[3]
address_a[4] => altsyncram_aa72:altsyncram1.address_a[4]
address_a[5] => altsyncram_aa72:altsyncram1.address_a[5]
address_a[6] => altsyncram_aa72:altsyncram1.address_a[6]
address_a[7] => altsyncram_aa72:altsyncram1.address_a[7]
clock0 => altsyncram_aa72:altsyncram1.clock0
q_a[0] <= altsyncram_aa72:altsyncram1.q_a[0]
q_a[1] <= altsyncram_aa72:altsyncram1.q_a[1]
q_a[2] <= altsyncram_aa72:altsyncram1.q_a[2]
q_a[3] <= altsyncram_aa72:altsyncram1.q_a[3]
q_a[4] <= altsyncram_aa72:altsyncram1.q_a[4]
q_a[5] <= altsyncram_aa72:altsyncram1.q_a[5]
q_a[6] <= altsyncram_aa72:altsyncram1.q_a[6]
q_a[7] <= altsyncram_aa72:altsyncram1.q_a[7]


|dds|date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[5] => ram_block3a4.PORTAADDR5
address_a[5] => ram_block3a5.PORTAADDR5
address_a[5] => ram_block3a6.PORTAADDR5
address_a[5] => ram_block3a7.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[6] => ram_block3a4.PORTAADDR6
address_a[6] => ram_block3a5.PORTAADDR6
address_a[6] => ram_block3a6.PORTAADDR6
address_a[6] => ram_block3a7.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_a[7] => ram_block3a4.PORTAADDR7
address_a[7] => ram_block3a5.PORTAADDR7
address_a[7] => ram_block3a6.PORTAADDR7
address_a[7] => ram_block3a7.PORTAADDR7
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.PORTBADDR
address_b[0] => ram_block3a7.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[1] => ram_block3a4.PORTBADDR1
address_b[1] => ram_block3a5.PORTBADDR1
address_b[1] => ram_block3a6.PORTBADDR1
address_b[1] => ram_block3a7.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[2] => ram_block3a4.PORTBADDR2
address_b[2] => ram_block3a5.PORTBADDR2
address_b[2] => ram_block3a6.PORTBADDR2
address_b[2] => ram_block3a7.PORTBADDR2
address_b[3] => ram_block3a0.PORTBADDR3
address_b[3] => ram_block3a1.PORTBADDR3
address_b[3] => ram_block3a2.PORTBADDR3
address_b[3] => ram_block3a3.PORTBADDR3
address_b[3] => ram_block3a4.PORTBADDR3
address_b[3] => ram_block3a5.PORTBADDR3
address_b[3] => ram_block3a6.PORTBADDR3
address_b[3] => ram_block3a7.PORTBADDR3
address_b[4] => ram_block3a0.PORTBADDR4
address_b[4] => ram_block3a1.PORTBADDR4
address_b[4] => ram_block3a2.PORTBADDR4
address_b[4] => ram_block3a3.PORTBADDR4
address_b[4] => ram_block3a4.PORTBADDR4
address_b[4] => ram_block3a5.PORTBADDR4
address_b[4] => ram_block3a6.PORTBADDR4
address_b[4] => ram_block3a7.PORTBADDR4
address_b[5] => ram_block3a0.PORTBADDR5
address_b[5] => ram_block3a1.PORTBADDR5
address_b[5] => ram_block3a2.PORTBADDR5
address_b[5] => ram_block3a3.PORTBADDR5
address_b[5] => ram_block3a4.PORTBADDR5
address_b[5] => ram_block3a5.PORTBADDR5
address_b[5] => ram_block3a6.PORTBADDR5
address_b[5] => ram_block3a7.PORTBADDR5