prev_cmp_dds.fit.qmsg

实现dds功能

{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "25 unused 3.30 4 21 0 " "Info: Number of I/O pins in group: 25 (unused VREF, 3.30 VCCIO, 4 input, 21 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 10 34 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 10 total pin(s) used --  34 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 4 45 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  45 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 1 47 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  47 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0}
{ "Warning" "WCUT_CUT_YGR_PLL_BAD_FANOUT_CLK3" "clk0 pllu:inst3\|altpll:altpll_component\|pll " "Warning: Output port clk0 of PLL \"pllu:inst3\|altpll:altpll_component\|pll\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "e:/tools/quartus/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } } { "pllu.vhd" "" { Text "C:/Documents and Settings/ff/桌面/123/pllu.vhd" 137 0 0 } } { "dds.bdf" "" { Schematic "C:/Documents and Settings/ff/桌面/123/dds.bdf" { { 48 120 384 208 "inst3" "" } } } }  } 0 0 "Output port %1!s! of PLL \"%2!s!\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:03 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:08 " "Info: Fitter placement operations ending: elapsed time is 00:00:08" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.689 ns memory register " "Info: Estimated most critical path is memory to register delay of 5.689 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns date_rom:inst10\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|ram_block3a7~porta_address_reg7 1 MEM M4K_X17_Y6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y6; Fanout = 1; MEM Node = 'date_rom:inst10\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|ram_block3a7~porta_address_reg7'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_address_reg7 } "NODE_NAME" } } { "db/altsyncram_aa72.tdf" "" { Text "C:/Documents and Settings/ff/桌面/123/db/altsyncram_aa72.tdf" 263 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns date_rom:inst10\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|q_a\[7\] 2 MEM M4K_X17_Y6 3 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X17_Y6; Fanout = 3; MEM Node = 'date_rom:inst10\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|q_a\[7\]'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.308 ns" { date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_address_reg7 date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|q_a[7] } "NODE_NAME" } } { "db/altsyncram_aa72.tdf" "" { Text "C:/Documents and Settings/ff/桌面/123/db/altsyncram_aa72.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.643 ns) + CELL(0.738 ns) 5.689 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[15\] 3 REG LAB_X20_Y6 3 " "Info: 3: + IC(0.643 ns) + CELL(0.738 ns) = 5.689 ns; Loc. = LAB_X20_Y6; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[15\]'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.381 ns" { date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|q_a[7] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[15] } "NODE_NAME" } } { "e:/tools/quartus/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/tools/quartus/quartus/libraries/megafunctions/sld_signaltap.vhd" 939 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.046 ns ( 88.70 % ) " "Info: Total cell delay = 5.046 ns ( 88.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.643 ns ( 11.30 % ) " "Info: Total interconnect delay = 0.643 ns ( 11.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.689 ns" { date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_address_reg7 date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|q_a[7] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[15] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}