dds.map.qmsg

实现dds功能

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d fword.vhd(28) " "Warning (10492): VHDL Process Statement warning at fword.vhd(28): signal \"d\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "fword.vhd" "" { Text "E:/temp/123/fword.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d fword.vhd(30) " "Warning (10492): VHDL Process Statement warning at fword.vhd(30): signal \"d\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "fword.vhd" "" { Text "E:/temp/123/fword.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d fword.vhd(32) " "Warning (10492): VHDL Process Statement warning at fword.vhd(32): signal \"d\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "fword.vhd" "" { Text "E:/temp/123/fword.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d fword.vhd(34) " "Warning (10492): VHDL Process Statement warning at fword.vhd(34): signal \"d\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "fword.vhd" "" { Text "E:/temp/123/fword.vhd" 34 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d fword.vhd(36) " "Warning (10492): VHDL Process Statement warning at fword.vhd(36): signal \"d\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "fword.vhd" "" { Text "E:/temp/123/fword.vhd" 36 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d fword.vhd(38) " "Warning (10492): VHDL Process Statement warning at fword.vhd(38): signal \"d\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "fword.vhd" "" { Text "E:/temp/123/fword.vhd" 38 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d fword.vhd(40) " "Warning (10492): VHDL Process Statement warning at fword.vhd(40): signal \"d\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "fword.vhd" "" { Text "E:/temp/123/fword.vhd" 40 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d fword.vhd(42) " "Warning (10492): VHDL Process Statement warning at fword.vhd(42): signal \"d\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "fword.vhd" "" { Text "E:/temp/123/fword.vhd" 42 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d fword.vhd(44) " "Warning (10492): VHDL Process Statement warning at fword.vhd(44): signal \"d\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "fword.vhd" "" { Text "E:/temp/123/fword.vhd" 44 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d fword.vhd(46) " "Warning (10492): VHDL Process Statement warning at fword.vhd(46): signal \"d\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "fword.vhd" "" { Text "E:/temp/123/fword.vhd" 46 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "fdip fword.vhd(26) " "Warning (10631): VHDL Process Statement warning at fword.vhd(26): inferring latch(es) for signal or variable \"fdip\", which holds its previous value in one or more paths through the process" {  } { { "fword.vhd" "" { Text "E:/temp/123/fword.vhd" 26 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "fdip\[0\] fword.vhd(26) " "Info (10041): Inferred latch for \"fdip\[0\]\" at fword.vhd(26)" {  } { { "fword.vhd" "" { Text "E:/temp/123/fword.vhd" 26 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "fdip\[1\] fword.vhd(26) " "Info (10041): Inferred latch for \"fdip\[1\]\" at fword.vhd(26)" {  } { { "fword.vhd" "" { Text "E:/temp/123/fword.vhd" 26 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "fdip\[2\] fword.vhd(26) " "Info (10041): Inferred latch for \"fdip\[2\]\" at fword.vhd(26)" {  } { { "fword.vhd" "" { Text "E:/temp/123/fword.vhd" 26 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "fdip\[3\] fword.vhd(26) " "Info (10041): Inferred latch for \"fdip\[3\]\" at fword.vhd(26)" {  } { { "fword.vhd" "" { Text "E:/temp/123/fword.vhd" 26 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "date_rom date_rom:inst2 " "Info: Elaborating entity \"date_rom\" for hierarchy \"date_rom:inst2\"" {  } { { "dds.bdf" "inst2" { Schematic "E:/temp/123/dds.bdf" { { 264 384 600 400 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../tools/quartus/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../tools/quartus/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "e:/tools/quartus/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram date_rom:inst2\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"date_rom:inst2\|altsyncram:altsyncram_component\"" {  } { { "date_rom.vhd" "altsyncram_component" { Text "E:/temp/123/date_rom.vhd" 83 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "date_rom:inst2\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"date_rom:inst2\|altsyncram:altsyncram_component\"" {  } { { "date_rom.vhd" "" { Text "E:/temp/123/date_rom.vhd" 83 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}