dds.tan.qmsg

实现dds功能

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "pllu:inst3\|altpll:altpll_component\|_clk0 register reg32b:inst1\|dout\[31\] register reg32b:inst1\|dout\[31\] 1.065 ns " "Info: Minimum slack time is 1.065 ns for clock \"pllu:inst3\|altpll:altpll_component\|_clk0\" between source register \"reg32b:inst1\|dout\[31\]\" and destination register \"reg32b:inst1\|dout\[31\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.856 ns + Shortest register register " "Info: + Shortest register to register delay is 0.856 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reg32b:inst1\|dout\[31\] 1 REG LC_X21_Y6_N5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y6_N5; Fanout = 3; REG Node = 'reg32b:inst1\|dout\[31\]'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { reg32b:inst1|dout[31] } "NODE_NAME" } } { "reg.vhd" "" { Text "E:/temp/123/reg.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.547 ns) + CELL(0.309 ns) 0.856 ns reg32b:inst1\|dout\[31\] 2 REG LC_X21_Y6_N5 3 " "Info: 2: + IC(0.547 ns) + CELL(0.309 ns) = 0.856 ns; Loc. = LC_X21_Y6_N5; Fanout = 3; REG Node = 'reg32b:inst1\|dout\[31\]'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.856 ns" { reg32b:inst1|dout[31] reg32b:inst1|dout[31] } "NODE_NAME" } } { "reg.vhd" "" { Text "E:/temp/123/reg.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 36.10 % ) " "Info: Total cell delay = 0.309 ns ( 36.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.547 ns ( 63.90 % ) " "Info: Total interconnect delay = 0.547 ns ( 63.90 % )" {  } {  } 0 0 "T