dds.tan.qmsg

实现dds功能

{ "Info" "ITDB_FULL_SLACK_RESULT" "clk memory date_rom:inst2\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|ram_block3a7~porta_address_reg7 register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[1\] -3.849 ns " "Info: Slack time is -3.849 ns for clock \"clk\" between source memory \"date_rom:inst2\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|ram_block3a7~porta_address_reg7\" and destination register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[1\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "1.736 ns + Largest memory register " "Info: + Largest memory to register requirement is 1.736 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "1.885 ns + " "Info: + Setup relationship between source and destination is 1.885 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 4.166 ns " "Info: + Latch edge is 4.166 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 20.833 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 20.833 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 2.281 ns " "Info: - Launch edge is 2.281 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pllu:inst3\|altpll:altpll_component\|_clk0 49.999 ns -1.885 ns  50 " "Info: Clock period of Source clock \"pllu:inst3\|altpll:altpll_component\|_clk0\" is 49.999 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.538 ns + Largest " "Info: + Largest clock skew is 0.538 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 334 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 334; CLK Node = 'clk'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.bdf" "" { Schematic "E:/temp/123/dds.bdf" { { 248 8 176 264 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[1\] 2 REG LC_X16_Y13_N1 3 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X16_Y13_N1; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[1\]'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] } "NODE_NAME" } } { "../../tools/quartus/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "E:/tools/quartus/quartus/libraries/megafunctions/sld_signaltap.vhd" 939 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pllu:inst3\|altpll:altpll_component\|_clk0 source 2.416 ns - Longest memory " "Info: - Longest clock path from clock \"pllu:inst3\|altpll:altpll_component\|_clk0\" to source memory is 2.416 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pllu:inst3\|altpll:altpll_component\|_clk0 1 CLK PLL_1 83 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 83; CLK Node = 'pllu:inst3\|altpll:altpll_component\|_clk0'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { pllu:inst3|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "e:/tools/quartus/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.694 ns) + CELL(0.722 ns) 2.416 ns date_rom:inst2\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|ram_block3a7~porta_address_reg7 2 MEM M4K_X17_Y13 8 " "Info: 2: + IC(1.694 ns) + CELL(0.722 ns) = 2.416 ns; Loc. = M4K_X17_Y13; Fanout = 8; MEM Node = 'date_rom:inst2\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|ram_block3a7~porta_address_reg7'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.416 ns" { pllu:inst3|altpll:altpll_component|_clk0 date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_address_reg7 } "NODE_NAME" } } { "db/altsyncram_aa72.tdf" "" { Text "E:/temp/123/db/altsyncram_aa72.tdf" 263 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.722 ns ( 29.88 % ) " "Info: Total cell delay = 0.722 ns ( 29.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.694 ns ( 70.12 % ) " "Info: Total interconnect delay = 1.694 ns ( 70.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.416 ns" { pllu:inst3|altpll:altpll_component|_clk0 date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_address_reg7 } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "2.416 ns" { pllu:inst3|altpll:altpll_component|_clk0 {} date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_address_reg7 {} } { 0.000ns 1.694ns } { 0.000ns 0.722ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.416 ns" { pllu:inst3|altpll:altpll_component|_clk0 date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_address_reg7 } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "2.416 ns" { pllu:inst3|altpll:altpll_component|_clk0 {} date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_address_reg7 {} } { 0.000ns 1.694ns } { 0.000ns 0.722ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns - " "Info: - Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_aa72.tdf" "" { Text "E:/temp/123/db/altsyncram_aa72.tdf" 263 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "../../tools/quartus/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "E:/tools/quartus/quartus/libraries/megafunctions/sld_signaltap.vhd" 939 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.416 ns" { pllu:inst3|altpll:altpll_component|_clk0 date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_address_reg7 } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "2.416 ns" { pllu:inst3|altpll:altpll_component|_clk0 {} date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_address_reg7 {} } { 0.000ns 1.694ns } { 0.000ns 0.722ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.585 ns - Longest memory register " "Info: - Longest memory to register delay is 5.585 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns date_rom:inst2\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|ram_block3a7~porta_address_reg7 1 MEM M4K_X17_Y13 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y13; Fanout = 8; MEM Node = 'date_rom:inst2\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|ram_block3a7~porta_address_reg7'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_address_reg7 } "NODE_NAME" } } { "db/altsyncram_aa72.tdf" "" { Text "E:/temp/123/db/altsyncram_aa72.tdf" 263 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns date_rom:inst2\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|q_a\[1\] 2 MEM M4K_X17_Y13 3 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X17_Y13; Fanout = 3; MEM Node = 'date_rom:inst2\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|q_a\[1\]'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.308 ns" { date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_address_reg7 date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|q_a[1] } "NODE_NAME" } } { "db/altsyncram_aa72.tdf" "" { Text "E:/temp/123/db/altsyncram_aa72.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.162 ns) + CELL(0.115 ns) 5.585 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[1\] 3 REG LC_X16_Y13_N1 3 " "Info: 3: + IC(1.162 ns) + CELL(0.115 ns) = 5.585 ns; Loc. = LC_X16_Y13_N1; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[1\]'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.277 ns" { date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|q_a[1] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] } "NODE_NAME" } } { "../../tools/quartus/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "E:/tools/quartus/quartus/libraries/megafunctions/sld_signaltap.vhd" 939 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.423 ns ( 79.19 % ) " "Info: Total cell delay = 4.423 ns ( 79.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.162 ns ( 20.81 % ) " "Info: Total interconnect delay = 1.162 ns ( 20.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.585 ns" { date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_address_reg7 date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|q_a[1] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "5.585 ns" { date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_address_reg7 {} date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|q_a[1] {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] {} } { 0.000ns 0.000ns 1.162ns } { 0.000ns 4.308ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.416 ns" { pllu:inst3|altpll:altpll_component|_clk0 date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_address_reg7 } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "2.416 ns" { pllu:inst3|altpll:altpll_component|_clk0 {} date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_address_reg7 {} } { 0.000ns 1.694ns } { 0.000ns 0.722ns } "" } } { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.585 ns" { date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_address_reg7 date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|q_a[1] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "5.585 ns" { date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_address_reg7 {} date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|q_a[1] {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] {} } { 0.000ns 0.000ns 1.162ns } { 0.000ns 4.308ns 0.115ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'clk' 256 " "Warning: Can't achieve timing requirement Clock Setup: 'clk' along 256 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[2\] register sld_hub:sld_hub_inst\|hub_tdo_reg 47.0 MHz 21.276 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 47.0 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[2\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo_reg\" (period= 21.276 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.377 ns + Longest register register " "Info: + Longest register to register delay is 10.377 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[2\] 1 REG LC_X11_Y13_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y13_N7; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[2\]'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[2] } "NODE_NAME" } } { "../../tools/quartus/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "E:/tools/quartus/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.304 ns) + CELL(0.590 ns) 1.894 ns sld_hub:sld_hub_inst\|node_ena~39 2 COMB LC_X11_Y11_N7 6 " "Info: 2: + IC(1.304 ns) + CELL(0.590 ns) = 1.894 ns; Loc. = LC_X11_Y11_N7; Fanout = 6; COMB Node = 'sld_hub:sld_hub_inst\|node_ena~39'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.894 ns" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[2] sld_hub:sld_hub_inst|node_ena~39 } "NODE_NAME" } } { "../../tools/quartus/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/tools/quartus/quartus/libraries/megafunctions/sld_hub.vhd" 136 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.144 ns) + CELL(0.590 ns) 3.628 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|crc_rom_sr_ena~31 3 COMB LC_X12_Y11_N8 5 " "Info: 3: + IC(1.144 ns) + CELL(0.590 ns) = 3.628 ns; Loc. = LC_X12_Y11_N8; Fanout = 5; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|crc_rom_sr_ena~31'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.734 ns" { sld_hub:sld_hub_inst|node_ena~39 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 } "NODE_NAME" } } { "../../tools/quartus/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "E:/tools/quartus/quartus/libraries/megafunctions/sld_signaltap.vhd" 803 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.398 ns) + CELL(0.442 ns) 4.468 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|status_shift_enable~62 4 COMB LC_X12_Y11_N6 18 " "Info: 4: + IC(0.398 ns) + CELL(0.442 ns) = 4.468 ns; Loc. = LC_X12_Y11_N6; Fanout = 18; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|status_shift_enable~62'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.840 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~62 } "NODE_NAME" } } { "../../tools/quartus/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "E:/tools/quartus/quartus/libraries/megafunctions/sld_signaltap.vhd" 831 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.114 ns) 5.016 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~425 5 COMB LC_X12_Y11_N3 1 " "Info: 5: + IC(0.434 ns) + CELL(0.114 ns) = 5.016 ns; Loc. = LC_X12_Y11_N3; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~425'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.548 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~62 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 } "NODE_NAME" } } { "../../tools/quartus/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "E:/tools/quartus/quartus/libraries/megafunctions/sld_signaltap.vhd" 512 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.686 ns) + CELL(0.114 ns) 5.816 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~428 6 COMB LC_X11_Y11_N3 1 " "Info: 6: + IC(0.686 ns) + CELL(0.114 ns) = 5.816 ns; Loc. = LC_X11_Y11_N3; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~428'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 } "NODE_NAME" } } { "../../tools/quartus/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "E:/tools/quartus/quartus/libraries/megafunctions/sld_signaltap.vhd" 512 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.408 ns) + CELL(0.442 ns) 6.666 ns sld_hub:sld_hub_inst\|hub_tdo_reg~438 7 COMB LC_X11_Y11_N1 1 " "Info: 7: + IC(0.408 ns) + CELL(0.442 ns) = 6.666 ns; Loc. = LC_X11_Y11_N1; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~438'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.850 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|hub_tdo_reg~438 } "NODE_NAME" } } { "../../tools/quartus/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/tools/quartus/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.254 ns) + CELL(0.114 ns) 8.034 ns sld_hub:sld_hub_inst\|hub_tdo_reg~439 8 COMB LC_X11_Y12_N1 1 " "Info: 8: + IC(1.254 ns) + CELL(0.114 ns) = 8.034 ns; Loc. = LC_X11_Y12_N1; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~439'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.368 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~438 sld_hub:sld_hub_inst|hub_tdo_reg~439 } "NODE_NAME" } } { "../../tools/quartus/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/tools/quartus/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.114 ns) 8.575 ns sld_hub:sld_hub_inst\|hub_tdo_reg~440 9 COMB LC_X11_Y12_N4 1 " "Info: 9: + IC(0.427 ns) + CELL(0.114 ns) = 8.575 ns; Loc. = LC_X11_Y12_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~440'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.541 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~439 sld_hub:sld_hub_inst|hub_tdo_reg~440 } "NODE_NAME" } } { "../../tools/quartus/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/tools/quartus/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.195 ns) + CELL(0.607 ns) 10.377 ns sld_hub:sld_hub_inst\|hub_tdo_reg 10 REG LC_X11_Y15_N6 2 " "Info: 10: + IC(1.195 ns) + CELL(0.607 ns) = 10.377 ns; Loc. = LC_X11_Y15_N6; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.802 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~440 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "../../tools/quartus/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/tools/quartus/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.127 ns ( 30.13 % ) " "Info: Total cell delay = 3.127 ns ( 30.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.250 ns ( 69.87 % ) " "Info: Total interconnect delay = 7.250 ns ( 69.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "10.377 ns" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[2] sld_hub:sld_hub_inst|node_ena~39 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~62 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|hub_tdo_reg~438 sld_hub:sld_hub_inst|hub_tdo_reg~439 sld_hub:sld_hub_inst|hub_tdo_reg~440 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "10.377 ns" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[2] {} sld_hub:sld_hub_inst|node_ena~39 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~62 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 {} sld_hub:sld_hub_inst|hub_tdo_reg~438 {} sld_hub:sld_hub_inst|hub_tdo_reg~439 {} sld_hub:sld_hub_inst|hub_tdo_reg~440 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 1.304ns 1.144ns 0.398ns 0.434ns 0.686ns 0.408ns 1.254ns 0.427ns 1.195ns } { 0.000ns 0.590ns 0.590ns 0.442ns 0.114ns 0.114ns 0.442ns 0.114ns 0.114ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.322 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.322 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 467 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 467; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.611 ns) + CELL(0.711 ns) 5.322 ns sld_hub:sld_hub_inst\|hub_tdo_reg 2 REG LC_X11_Y15_N6 2 " "Info: 2: + IC(4.611 ns) + CELL(0.711 ns) = 5.322 ns; Loc. = LC_X11_Y15_N6; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.322 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "../../tools/quartus/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/tools/quartus/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.36 % ) " "Info: Total cell delay = 0.711 ns ( 13.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.611 ns ( 86.64 % ) " "Info: Total interconnect delay = 4.611 ns ( 86.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.322 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "5.322 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 4.611ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.322 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.322 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 467 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 467; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.611 ns) + CELL(0.711 ns) 5.322 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[2\] 2 REG LC_X11_Y13_N7 4 " "Info: 2: + IC(4.611 ns) + CELL(0.711 ns) = 5.322 ns; Loc. = LC_X11_Y13_N7; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[2\]'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.322 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[2] } "NODE_NAME" } } { "../../tools/quartus/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "E:/tools/quartus/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.36 % ) " "Info: Total cell delay = 0.711 ns ( 13.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.611 ns ( 86.64 % ) " "Info: Total interconnect delay = 4.611 ns ( 86.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.322 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[2] } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "5.322 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[2] {} } { 0.000ns 4.611ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.322 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "5.322 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 4.611ns } { 0.000ns 0.711ns } "" } } { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.322 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[2] } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "5.322 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[2] {} } { 0.000ns 4.611ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../../tools/quartus/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "E:/tools/quartus/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../../tools/quartus/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/tools/quartus/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "../../tools/quartus/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "E:/tools/quartus/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "../../tools/quartus/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/tools/quartus/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "10.377 ns" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[2] sld_hub:sld_hub_inst|node_ena~39 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~62 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|hub_tdo_reg~438 sld_hub:sld_hub_inst|hub_tdo_reg~439 sld_hub:sld_hub_inst|hub_tdo_reg~440 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "10.377 ns" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[2] {} sld_hub:sld_hub_inst|node_ena~39 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~62 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 {} sld_hub:sld_hub_inst|hub_tdo_reg~438 {} sld_hub:sld_hub_inst|hub_tdo_reg~439 {} sld_hub:sld_hub_inst|hub_tdo_reg~440 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 1.304ns 1.144ns 0.398ns 0.434ns 0.686ns 0.408ns 1.254ns 0.427ns 1.195ns } { 0.000ns 0.590ns 0.590ns 0.442ns 0.114ns 0.114ns 0.442ns 0.114ns 0.114ns 0.607ns } "" } } { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.322 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "5.322 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 4.611ns } { 0.000ns 0.711ns } "" } } { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.322 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[2] } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "5.322 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[2] {} } { 0.000ns 4.611ns } { 0.000ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}