dds.tan.qmsg

实现dds功能

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "pword:inst11\|clkcnt2\[9\] " "Info: Detected ripple clock \"pword:inst11\|clkcnt2\[9\]\" as buffer" {  } { { "pword.vhd" "" { Text "E:/temp/123/pword.vhd" 55 -1 0 } } { "e:/tools/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/tools/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "pword:inst11\|clkcnt2\[9\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "pllu:inst3\|altpll:altpll_component\|_clk0 memory date_rom:inst10\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|ram_block3a7~porta_datain_reg7 memory date_rom:inst10\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|ram_block3a7~porta_memory_reg7 44.923 ns " "Info: Slack time is 44.923 ns for clock \"pllu:inst3\|altpll:altpll_component\|_clk0\" between source memory \"date_rom:inst10\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|ram_block3a7~porta_datain_reg7\" and destination memory \"date_rom:inst10\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|ram_block3a7~porta_memory_reg7\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "197.01 MHz 5.076 ns " "Info: Fmax is 197.01 MHz (period= 5.076 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "49.242 ns + Largest memory memory " "Info: + Largest memory to memory requirement is 49.242 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "49.999 ns + " "Info: + Setup relationship between source and destination is 49.999 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 48.114 ns " "Info: + Latch edge is 48.114 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pllu:inst3\|altpll:altpll_component\|_clk0 49.999 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"pllu:inst3\|altpll:altpll_component\|_clk0\" is 49.999 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.885 ns " "Info: - Launch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pllu:inst3\|altpll:altpll_component\|_clk0 49.999 ns -1.885 ns  50 " "Info: Clock period of Source clock \"pllu:inst3\|altpll:altpll_component\|_clk0\" is 49.999 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns + Largest " "Info: + Largest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pllu:inst3\|altpll:altpll_component\|_clk0 destination 2.349 ns + Shortest memory " "Info: + Shortest clock path from clock \"pllu:inst3\|altpll:altpll_component\|_clk0\" to destination memory is 2.349 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pllu:inst3\|altpll:altpll_component\|_clk0 1 CLK PLL_1 83 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 83; CLK Node = 'pllu:inst3\|altpll:altpll_component\|_clk0'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { pllu:inst3|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "e:/tools/quartus/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.641 ns) + CELL(0.708 ns) 2.349 ns date_rom:inst10\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|ram_block3a7~porta_memory_reg7 2 MEM M4K_X17_Y6 0 " "Info: 2: + IC(1.641 ns) + CELL(0.708 ns) = 2.349 ns; Loc. = M4K_X17_Y6; Fanout = 0; MEM Node = 'date_rom:inst10\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|ram_block3a7~porta_memory_reg7'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { pllu:inst3|altpll:altpll_component|_clk0 date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } } { "db/altsyncram_aa72.tdf" "" { Text "E:/temp/123/db/altsyncram_aa72.tdf" 263 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.708 ns ( 30.14 % ) " "Info: Total cell delay = 0.708 ns ( 30.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.641 ns ( 69.86 % ) " "Info: Total interconnect delay = 1.641 ns ( 69.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { pllu:inst3|altpll:altpll_component|_clk0 date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { pllu:inst3|altpll:altpll_component|_clk0 {} date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg7 {} } { 0.000ns 1.641ns } { 0.000ns 0.708ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pllu:inst3\|altpll:altpll_component\|_clk0 source 2.363 ns - Longest memory " "Info: - Longest clock path from clock \"pllu:inst3\|altpll:altpll_component\|_clk0\" to source memory is 2.363 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pllu:inst3\|altpll:altpll_component\|_clk0 1 CLK PLL_1 83 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 83; CLK Node = 'pllu:inst3\|altpll:altpll_component\|_clk0'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { pllu:inst3|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "e:/tools/quartus/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.641 ns) + CELL(0.722 ns) 2.363 ns date_rom:inst10\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|ram_block3a7~porta_datain_reg7 2 MEM M4K_X17_Y6 1 " "Info: 2: + IC(1.641 ns) + CELL(0.722 ns) = 2.363 ns; Loc. = M4K_X17_Y6; Fanout = 1; MEM Node = 'date_rom:inst10\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|ram_block3a7~porta_datain_reg7'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.363 ns" { pllu:inst3|altpll:altpll_component|_clk0 date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg7 } "NODE_NAME" } } { "db/altsyncram_aa72.tdf" "" { Text "E:/temp/123/db/altsyncram_aa72.tdf" 263 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.722 ns ( 30.55 % ) " "Info: Total cell delay = 0.722 ns ( 30.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.641 ns ( 69.45 % ) " "Info: Total interconnect delay = 1.641 ns ( 69.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.363 ns" { pllu:inst3|altpll:altpll_component|_clk0 date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg7 } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "2.363 ns" { pllu:inst3|altpll:altpll_component|_clk0 {} date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg7 {} } { 0.000ns 1.641ns } { 0.000ns 0.722ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { pllu:inst3|altpll:altpll_component|_clk0 date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { pllu:inst3|altpll:altpll_component|_clk0 {} date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg7 {} } { 0.000ns 1.641ns } { 0.000ns 0.708ns } "" } } { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.363 ns" { pllu:inst3|altpll:altpll_component|_clk0 date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg7 } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "2.363 ns" { pllu:inst3|altpll:altpll_component|_clk0 {} date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg7 {} } { 0.000ns 1.641ns } { 0.000ns 0.722ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns - " "Info: - Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_aa72.tdf" "" { Text "E:/temp/123/db/altsyncram_aa72.tdf" 263 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns - " "Info: - Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_aa72.tdf" "" { Text "E:/temp/123/db/altsyncram_aa72.tdf" 263 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { pllu:inst3|altpll:altpll_component|_clk0 date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { pllu:inst3|altpll:altpll_component|_clk0 {} date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg7 {} } { 0.000ns 1.641ns } { 0.000ns 0.708ns } "" } } { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.363 ns" { pllu:inst3|altpll:altpll_component|_clk0 date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg7 } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "2.363 ns" { pllu:inst3|altpll:altpll_component|_clk0 {} date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg7 {} } { 0.000ns 1.641ns } { 0.000ns 0.722ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns - Longest memory memory " "Info: - Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns date_rom:inst10\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|ram_block3a7~porta_datain_reg7 1 MEM M4K_X17_Y6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y6; Fanout = 1; MEM Node = 'date_rom:inst10\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|ram_block3a7~porta_datain_reg7'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg7 } "NODE_NAME" } } { "db/altsyncram_aa72.tdf" "" { Text "E:/temp/123/db/altsyncram_aa72.tdf" 263 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns date_rom:inst10\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|ram_block3a7~porta_memory_reg7 2 MEM M4K_X17_Y6 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X17_Y6; Fanout = 0; MEM Node = 'date_rom:inst10\|altsyncram:altsyncram_component\|altsyncram_tr51:auto_generated\|altsyncram_aa72:altsyncram1\|ram_block3a7~porta_memory_reg7'" {  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg7 date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } } { "db/altsyncram_aa72.tdf" "" { Text "E:/temp/123/db/altsyncram_aa72.tdf" 263 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg7 date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "4.319 ns" { date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg7 {} date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg7 {} } { 0.000ns 0.000ns } { 0.000ns 4.319ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { pllu:inst3|altpll:altpll_component|_clk0 date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { pllu:inst3|altpll:altpll_component|_clk0 {} date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg7 {} } { 0.000ns 1.641ns } { 0.000ns 0.708ns } "" } } { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.363 ns" { pllu:inst3|altpll:altpll_component|_clk0 date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg7 } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "2.363 ns" { pllu:inst3|altpll:altpll_component|_clk0 {} date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg7 {} } { 0.000ns 1.641ns } { 0.000ns 0.722ns } "" } } { "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg7 date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } } { "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/quartus/quartus/bin/Technology_Viewer.qrui" "4.319 ns" { date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg7 {} date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg7 {} } { 0.000ns 0.000ns } { 0.000ns 4.319ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}