dds.tan.qmsg

实现dds功能

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "fword:inst9\|fdip\[2\] " "Warning: Node \"fword:inst9\|fdip\[2\]\" is a latch" {  } { { "fword.vhd" "" { Text "E:/temp/123/fword.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "fword:inst9\|fdip\[3\] " "Warning: Node \"fword:inst9\|fdip\[3\]\" is a latch" {  } { { "fword.vhd" "" { Text "E:/temp/123/fword.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "fword:inst9\|fdip\[1\] " "Warning: Node \"fword:inst9\|fdip\[1\]\" is a latch" {  } { { "fword.vhd" "" { Text "E:/temp/123/fword.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "fword:inst9\|fdip\[0\] " "Warning: Node \"fword:inst9\|fdip\[0\]\" is a latch" {  } { { "fword.vhd" "" { Text "E:/temp/123/fword.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "pword:inst11\|pdip\[0\] " "Warning: Node \"pword:inst11\|pdip\[0\]\" is a latch" {  } { { "pword.vhd" "" { Text "E:/temp/123/pword.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "pword:inst11\|pdip\[1\] " "Warning: Node \"pword:inst11\|pdip\[1\]\" is a latch" {  } { { "pword.vhd" "" { Text "E:/temp/123/pword.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "pword:inst11\|pdip\[2\] " "Warning: Node \"pword:inst11\|pdip\[2\]\" is a latch" {  } { { "pword.vhd" "" { Text "E:/temp/123/pword.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "pword:inst11\|pdip\[3\] " "Warning: Node \"pword:inst11\|pdip\[3\]\" is a latch" {  } { { "pword.vhd" "" { Text "E:/temp/123/pword.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "e:/tools/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/tools/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}