reg.vhd

实现dds功能

library ieee;
use ieee.std_logic_1164.all;
entity reg32b is
port(load : in std_logic;
      din : in std_logic_vector(31 downto 0);
      dout:  out std_logic_vector(31 downto 0));
end reg32b;
architecture behav OF reg32b is
begin
process(load,din)
begin
if load'event and load='1'then
dout<=din;
end if;
end process;
end behav;