add.vhd

来自「实现dds功能」· VHDL 代码 · 共 12 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder32b is
port(A:in std_logic_vector(31 downto 0);
     B:in std_logic_vector(31 downto 0);
     S:out std_logic_vector(31 downto 0));
end adder32b;
architecture behav OF adder32b is
begin
S<=A+B;
end behav;