dds.tan.summary

实现dds功能

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.205 ns
From           : ps2_clk
To             : pword:inst11|dat[4]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 14.313 ns
From           : fword:inst9|code[3]
To             : code[3]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 7.535 ns
From           : dip
To             : altera_auto_signaltap_0_dip_ae
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.714 ns
From           : altera_internal_jtag~TDIUTAP
To             : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|lpm_shiftreg:status_register|dffs[16]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : -3.849 ns
Required Time  : 48.00 MHz ( period = 20.833 ns )
Actual Time    : N/A
From           : date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_address_reg7
To             : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1]
From Clock     : pllu:inst3|altpll:altpll_component|_clk0
To Clock       : clk
Failed Paths   : 256

Type           : Clock Setup: 'pllu:inst3|altpll:altpll_component|_clk0'
Slack          : 44.923 ns
Required Time  : 20.00 MHz ( period = 49.999 ns )
Actual Time    : 197.01 MHz ( period = 5.076 ns )
From           : date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg7
To             : date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg7
From Clock     : pllu:inst3|altpll:altpll_component|_clk0
To Clock       : pllu:inst3|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 47.00 MHz ( period = 21.276 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[2]
To             : sld_hub:sld_hub_inst|hub_tdo_reg
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : 0.822 ns
Required Time  : 48.00 MHz ( period = 20.833 ns )
Actual Time    : N/A
From           : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address[0]
To             : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address[0]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'pllu:inst3|altpll:altpll_component|_clk0'
Slack          : 1.065 ns
Required Time  : 20.00 MHz ( period = 49.999 ns )
Actual Time    : N/A
From           : reg32b:inst1|dout[31]
To             : reg32b:inst1|dout[31]
From Clock     : pllu:inst3|altpll:altpll_component|_clk0
To Clock       : pllu:inst3|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 256

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