dds.map.rpt

实现dds功能

Analysis & Synthesis report for dds
Wed Jun 18 22:04:00 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |dds|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state
  9. User-Specified and Inferred Latches
 10. Registers Removed During Synthesis
 11. Registers Protected by Synthesis
 12. General Register Statistics
 13. Inverted Register Statistics
 14. Multiplexer Restructuring Statistics (Restructuring Performed)
 15. Source assignments for date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1
 16. Source assignments for date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
 17. Source assignments for date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1
 18. Source assignments for date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
 19. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body
 20. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity
 21. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_qvo3:auto_generated
 22. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:\adv_point_3_and_more:advance_pointer_counter
 23. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:read_pointer_counter
 24. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:status_advance_pointer_counter
 25. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:status_read_pointer_counter
 26. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr
 27. Source assignments for sld_hub:sld_hub_inst
 28. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 29. Parameter Settings for User Entity Instance: pllu:inst3|altpll:altpll_component
 30. Parameter Settings for User Entity Instance: date_rom:inst2|altsyncram:altsyncram_component
 31. Parameter Settings for User Entity Instance: date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|sld_mod_ram_rom:mgl_prim2
 32. Parameter Settings for User Entity Instance: date_rom:inst10|altsyncram:altsyncram_component
 33. Parameter Settings for User Entity Instance: date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|sld_mod_ram_rom:mgl_prim2
 34. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 35. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 36. SignalTap II Logic Analyzer Settings
 37. In-System Memory Content Editor Settings
 38. Analysis & Synthesis Messages



----------------
; Legal Notice ;
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Copyright (C) 1991-2007 Altera Corporation
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