cyclone_atoms.vhd

一个非常好的dc使用书籍 一个非常好的dc使用书籍

                                          inverta_dataa)); 
          else
            icomb := VitalMUX(data => lut_mask_std,
                              dselect => (datad_ipd,
                                          cin1_ipd,
                                          datab_ipd,
                                          inverta_dataa)); 
          end if;
        end if;
      else
        icomb := VitalMUX(data => lut_mask_std,
                          dselect => (datad_ipd,
                                      cin_ipd,
                                      datab_ipd,
                                      inverta_dataa)); 
      end if;
    elsif sum_lutc_input = "qfbk" then
      icomb := VitalMUX(data => lut_mask_std,
                        dselect => (datad_ipd,
                                    qfbkin,
                                    datab_ipd,
                                    inverta_dataa)); 
    end if;
  end if;
  
  if operation_mode = "arithmetic" then
    if sum_lutc_input = "datac" then
      icomb := VitalMUX(data => lut_mask_std,
                        dselect => ('1',
                                    datac_ipd,
                                    datab_ipd,
                                    inverta_dataa));
    elsif sum_lutc_input = "cin" then
      if ((cin0_used = "true") or (cin1_used = "true")) then
        if cin_used = "true" then
          if (cin_ipd = '0') then
            icomb := VitalMUX(data => lut_mask_std,
                              dselect => ('1',
                                          cin0_ipd,
                                          datab_ipd,
                                          inverta_dataa)); 
          else
            icomb := VitalMUX(data => lut_mask_std,
                              dselect => ('1',
                                          cin1_ipd,
                                          datab_ipd,
                                          inverta_dataa)); 
          end if;
        else   -- cin is not used, inverta is used instead
          if (inverta_ipd = '0') then
            icomb := VitalMUX(data => lut_mask_std,
                              dselect => ('1',
                                          cin0_ipd,
                                          datab_ipd,
                                          inverta_dataa)); 
          else
            icomb := VitalMUX(data => lut_mask_std,
                              dselect => ('1',
                                          cin1_ipd,
                                          datab_ipd,
                                          inverta_dataa)); 
          end if;
        end if;
      else
        if cin_used = "true" then
          icomb := VitalMUX(data => lut_mask_std,
                            dselect => ('1',
                                        cin_ipd,
                                        datab_ipd,
                                        inverta_dataa)); 
        else  -- cin is not used, inverta is used in its place
          icomb := VitalMUX(data => lut_mask_std,
                            dselect => ('1',
                                        inverta_ipd,
                                        datab_ipd,
                                        inverta_dataa)); 
        end if;
      end if;
    elsif sum_lutc_input = "qfbk" then
      icomb := VitalMUX(data => lut_mask_std,
                        dselect => ('1',
                                    qfbkin,
                                    datab_ipd,
                                    inverta_dataa)); 
    end if;  -- end sum LUT
    
    -- carry lut
    icout0 := VitalMUX(data => lut_mask_std,
                       dselect => ('0',
                                   cin0_ipd,
                                   datab_ipd,
                                   inverta_dataa));
    icout1 := VitalMUX(data => lut_mask_std,
                       dselect => ('0',
                                   cin1_ipd,
                                   datab_ipd,
                                   inverta_dataa));
    if cin_used = "true" then 
      if (cin_ipd = '0') then
        icout := icout0;
      else
        icout := icout1;
      end if;
    else   -- inverta is used in place of cin
      if (inverta_ipd = '0') then
        icout := icout0;
      else
        icout := icout1;
      end if;	
    end if;
  end if;

  -- temp outputs
  tmp_combout := icomb;
  tmp_regin := icomb;
  tmp_cout := icout;
  tmp_cout0 := icout0;
  tmp_cout1 := icout1;

      ----------------------
      --  Path Delay Section
      ----------------------

      VitalPathDelay01 (
       OutSignal => combout,
       OutSignalName => "COMBOUT",
       OutTemp => tmp_combout,
       Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
                 1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
                 2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
                 3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
                 4 => (cin_ipd'last_event, tpd_cin_combout, TRUE),
                 5 => (cin0_ipd'last_event, tpd_cin0_combout, TRUE),
                 6 => (cin1_ipd'last_event, tpd_cin1_combout, TRUE),
                 7 => (inverta_ipd'last_event, tpd_inverta_combout, TRUE),
                 8 => (qfbkin'last_event, tpd_qfbkin_combout, TRUE)),
       GlitchData => combout_VitalGlitchData,
       Mode => DefGlitchMode,
       XOn  => XOn,
       MsgOn => MsgOn );

      VitalPathDelay01 (
       OutSignal => regin,
       OutSignalName => "REGIN",
       OutTemp => tmp_regin,
       Paths => (0 => (dataa_ipd'last_event, tpd_dataa_regin, TRUE),
                 1 => (datab_ipd'last_event, tpd_datab_regin, TRUE),
                 2 => (datac_ipd'last_event, tpd_datac_regin, TRUE),
                 3 => (datad_ipd'last_event, tpd_datad_regin, TRUE),
                 4 => (cin_ipd'last_event, tpd_cin_regin, TRUE),
                 5 => (cin0_ipd'last_event, tpd_cin0_regin, TRUE),
                 6 => (cin1_ipd'last_event, tpd_cin1_regin, TRUE),
                 7 => (inverta_ipd'last_event, tpd_inverta_regin, TRUE),
                 8 => (qfbkin'last_event, tpd_qfbkin_regin, TRUE)),
       GlitchData => regin_VitalGlitchData,
       Mode => DefGlitchMode,
       XOn  => XOn,
       MsgOn => MsgOn );

      VitalPathDelay01 ( 
       OutSignal => cout, 
       OutSignalName => "COUT",
       OutTemp => tmp_cout,
       Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
                 1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
                 2 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
                 3 => (cin0_ipd'last_event, tpd_cin0_cout, TRUE),
                 4 => (cin1_ipd'last_event, tpd_cin1_cout, TRUE),
                 5 => (inverta_ipd'last_event, tpd_inverta_cout, TRUE)),
       GlitchData => cout_VitalGlitchData,    
       Mode => DefGlitchMode, 
       XOn  => XOn, 
       MsgOn => MsgOn );

      VitalPathDelay01 ( 
       OutSignal => cout0, 
       OutSignalName => "COUT0",
       OutTemp => tmp_cout0,
       Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout0, TRUE),
                 1 => (datab_ipd'last_event, tpd_datab_cout0, TRUE),
                 2 => (cin0_ipd'last_event, tpd_cin0_cout0, TRUE),
                 3 => (inverta_ipd'last_event, tpd_inverta_cout0, TRUE)),
       GlitchData => cout0_VitalGlitchData,    
       Mode => DefGlitchMode, 
       XOn  => XOn, 
       MsgOn => MsgOn );

      VitalPathDelay01 ( 
       OutSignal => cout1, 
       OutSignalName => "COUT1",
       OutTemp => tmp_cout1,
       Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout1, TRUE),
                 1 => (datab_ipd'last_event, tpd_datab_cout1, TRUE),
                 2 => (cin1_ipd'last_event, tpd_cin1_cout1, TRUE),
                 3 => (inverta_ipd'last_event, tpd_inverta_cout1, TRUE)),
       GlitchData => cout1_VitalGlitchData,    
       Mode => DefGlitchMode, 
       XOn  => XOn, 
       MsgOn => MsgOn );
end process;

end vital_le;	

library IEEE, cyclone;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use cyclone.atom_pack.all;

entity cyclone_lcell_register is
  generic (
    synch_mode : string := "off";
    register_cascade_mode : string := "off";
    power_up : string := "low";
    x_on_violation : string := "on";

    TimingChecksOn: Boolean := True;
    MsgOn: Boolean := DefGlitchMsgOn;
    XOn: Boolean := DefGlitchXOn;
    MsgOnChecks: Boolean := DefMsgOnChecks;
    XOnChecks: Boolean := DefXOnChecks;
    InstancePath: STRING := "*";
    
    tsetup_regcascin_clk_noedge_posedge	: VitalDelayType := DefSetupHoldCnst;
    tsetup_datain_clk_noedge_posedge	: VitalDelayType := DefSetupHoldCnst;
    tsetup_datac_clk_noedge_posedge	: VitalDelayType := DefSetupHoldCnst;
    tsetup_sclr_clk_noedge_posedge	: VitalDelayType := DefSetupHoldCnst;
    tsetup_sload_clk_noedge_posedge	: VitalDelayType := DefSetupHoldCnst;
    tsetup_ena_clk_noedge_posedge	: VitalDelayType := DefSetupHoldCnst;
    thold_regcascin_clk_noedge_posedge	: VitalDelayType := DefSetupHoldCnst;
    thold_datain_clk_noedge_posedge	: VitalDelayType := DefSetupHoldCnst;
    thold_datac_clk_noedge_posedge	: VitalDelayType := DefSetupHoldCnst;
    thold_sclr_clk_noedge_posedge	: VitalDelayType := DefSetupHoldCnst;
    thold_sload_clk_noedge_posedge	: VitalDelayType := DefSetupHoldCnst;
    thold_ena_clk_noedge_posedge	: VitalDelayType := DefSetupHoldCnst;
    tpd_clk_regout_posedge		: VitalDelayType01 := DefPropDelay01;
    tpd_aclr_regout_posedge		: VitalDelayType01 := DefPropDelay01;
    tpd_aload_regout_posedge		: VitalDelayType01 := DefPropDelay01;
    tpd_datac_regout			: VitalDelayType01 := DefPropDelay01;
    tpd_clk_qfbkout_posedge		: VitalDelayType01 := DefPropDelay01;
    tpd_aclr_qfbkout_posedge		: VitalDelayType01 := DefPropDelay01;
    tpd_aload_qfbkout_posedge		: VitalDelayType01 := DefPropDelay01;
    tpd_datac_qfbkout			: VitalDelayType01 := DefPropDelay01;
    
    tipd_clk                            : VitalDelayType01 := DefPropDelay01;
    tipd_datac  			: VitalDelayType01 := DefPropDelay01;
    tipd_regcascin                      : VitalDelayType01 := DefPropDelay01; 
    tipd_ena                            : VitalDelayType01 := DefPropDelay01; 
    tipd_aclr                           : VitalDelayType01 := DefPropDelay01; 
    tipd_aload                          : VitalDelayType01 := DefPropDelay01; 
    tipd_sclr                           : VitalDelayType01 := DefPropDelay01; 
    tipd_sload                          : VitalDelayType01 := DefPropDelay01);
  
  port (clk     : in std_logic := '0';
        datain  : in std_logic := '0';
        datac   : in std_logic := '0';
        regcascin : in std_logic := '0';
        aclr    : in std_logic := '0';
        aload   : in std_logic := '0';
        sclr    : in std_logic := '0';
        sload   : in std_logic := '0';
        ena     : in std_logic := '1';
        devclrn : in std_logic := '1';
        devpor  : in std_logic := '1';
        regout  : out std_logic;
        qfbkout : out std_logic);
   attribute VITAL_LEVEL0 of cyclone_lcell_register : entity is TRUE;
end cyclone_lcell_register;
        
architecture vital_le_reg of cyclone_lcell_register is
   attribute VITAL_LEVEL0 of vital_le_reg : architecture is TRUE;
   signal ena_ipd, sload_ipd, aload_ipd, datac_ipd, regcascin_ipd : std_logic;
   signal clk_ipd, aclr_ipd, sclr_ipd : std_logic;
begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (datac_ipd, datac, tipd_datac);
   VitalWireDelay (clk_ipd, clk, tipd_clk);
   VitalWireDelay (regcascin_ipd, regcascin, tipd_regcascin);
   VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
   VitalWireDelay (aload_ipd, aload, tipd_aload);
   VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
   VitalWireDelay (sload_ipd, sload, tipd_sload);
   VitalWireDelay (ena_ipd, ena, tipd_ena);
   end block;

VITALtiming : process(clk_ipd, aclr_ipd, aload_ipd, datac_ipd,
                      devclrn, devpor, regcascin_ipd, datain,
                      sclr_ipd, ena_ipd, sload_ipd)

variable Tviol_regcascin_clk : std_ulogic := '0';
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_datac_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_regcascin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_datac_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable qfbkout_VitalGlitchData : VitalGlitchDataType;

variable iregout : std_logic;
variable idata: std_logic := '0';
variable tmp_regout : std_logic;
variable tmp_qfbkout : std_logic;

-- variables for 'X' generation
variable violation : std_logic := '0';

begin
  
  if (now = 0 ns) then
    if (power_up = "low") then
      iregout := '0';
    elsif (power_up = "high") then
      iregout := '1';
    end if;
  end if;

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then

         VitalSetupHoldCheck (
                Violation       => Tviol_datain_clk,
                TimingData      => TimingData_datain_clk,
                TestSignal      => datain,
                TestSignalName  => "DATAIN",
                RefSignal       => clk_ipd,