📄 cyclone_components.vhd
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vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USE PARAMETERS
m_initial : integer := 1;
m : integer := 1;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
l0_high : integer := 1;
l0_low : integer := 1;
l0_initial : integer := 1;
l0_mode : string := "bypass";
l0_ph : integer := 0;
l0_time_delay : integer := 0;
l1_high : integer := 1;
l1_low : integer := 1;
l1_initial : integer := 1;
l1_mode : string := "bypass";
l1_ph : integer := 0;
l1_time_delay : integer := 0;
g0_high : integer := 1;
g0_low : integer := 1;
g0_initial : integer := 1;
g0_mode : string := "bypass";
g0_ph : integer := 0;
g0_time_delay : integer := 0;
g1_high : integer := 1;
g1_low : integer := 1;
g1_initial : integer := 1;
g1_mode : string := "bypass";
g1_ph : integer := 0;
g1_time_delay : integer := 0;
g2_high : integer := 1;
g2_low : integer := 1;
g2_initial : integer := 1;
g2_mode : string := "bypass";
g2_ph : integer := 0;
g2_time_delay : integer := 0;
g3_high : integer := 1;
g3_low : integer := 1;
g3_initial : integer := 1;
g3_mode : string := "bypass";
g3_ph : integer := 0;
g3_time_delay : integer := 0;
e0_high : integer := 1;
e0_low : integer := 1;
e0_initial : integer := 1;
e0_mode : string := "bypass";
e0_ph : integer := 0;
e0_time_delay : integer := 0;
e1_high : integer := 1;
e1_low : integer := 1;
e1_initial : integer := 1;
e1_mode : string := "bypass";
e1_ph : integer := 0;
e1_time_delay : integer := 0;
e2_high : integer := 1;
e2_low : integer := 1;
e2_initial : integer := 1;
e2_mode : string := "bypass";
e2_ph : integer := 0;
e2_time_delay : integer := 0;
e3_high : integer := 1;
e3_low : integer := 1;
e3_initial : integer := 1;
e3_mode : string := "bypass";
e3_ph : integer := 0;
e3_time_delay : integer := 0;
m_ph : integer := 0;
m_time_delay : integer := 0;
n_time_delay : integer := 0;
extclk0_counter : string := "e0";
extclk1_counter : string := "e1";
extclk2_counter : string := "e2";
extclk3_counter : string := "e3";
clk0_counter : string := "g0";
clk1_counter : string := "g1";
clk2_counter : string := "g2";
clk3_counter : string := "g3";
clk4_counter : string := "l0";
clk5_counter : string := "l1";
enable0_counter : string := "l0";
enable1_counter : string := "l0";
charge_pump_current : integer := 0;
loop_filter_c : integer := 1;
loop_filter_r : string := "1.0" ;
pll_compensation_delay : integer := 0;
simulation_type : string := "timing";
source_is_pll : string := "off";
skip_vco : string := "off";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkena : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_extclkena : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanaclr : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_comparator : VitalDelayType01 := DefPropDelay01
);
PORT (inclk : IN std_logic_vector(1 downto 0);
fbin : IN std_logic := '0';
ena : IN std_logic := '1';
clkswitch : IN std_logic := '0';
areset : IN std_logic := '0';
pfdena : IN std_logic := '1';
clkena : IN std_logic_vector(5 downto 0) := "111111";
extclkena : IN std_logic_vector(3 downto 0) := "1111";
scanaclr : IN std_logic := '0';
scandata : IN std_logic := '0';
scanclk : IN std_logic := '0';
clk : OUT std_logic_vector(5 downto 0);
extclk : OUT std_logic_vector(3 downto 0);
clkbad : OUT std_logic_vector(1 downto 0);
activeclock : OUT std_logic;
locked : OUT std_logic;
clkloss : OUT std_logic;
scandataout : OUT std_logic;
-- lvds specific ports
comparator : IN std_logic := '0';
enable0 : OUT std_logic;
enable1 : OUT std_logic
);
END COMPONENT;
--
-- CYCLONE_DLL
--
COMPONENT cyclone_dll
GENERIC ( input_frequency : integer := 10000;
phase_shift : integer := 0;
sim_valid_lock : integer := 1;
sim_invalid_lock : integer := 5
);
PORT (clk : IN std_logic;
devclrn : IN std_logic;
devpor : IN std_logic;
delayctrlout : OUT std_logic
);
END COMPONENT;
--
-- CYCLONE_JTAG
--
component cyclone_jtag
port (tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic);
end component;
--
--
-- CYCLONE_CRCBLOCK
--
--
component cyclone_crcblock
generic (
oscillator_divider : integer := 1
);
port (clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic);
end component;
--
-- CYCLONE_IO
--
component cyclone_io
generic (
operation_mode : string := "input";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_sync_reset : string := "none";
output_power_up : string := "low";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_sync_reset : string := "none";
oe_power_up : string := "low";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_sync_reset : string := "none";
input_power_up : string := "low");
port (
datain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
combout : out std_logic;
regout : out std_logic;
padio : inout std_logic);
end component;
--
-- CYCLONE_ASMIBLOCK
--
component cyclone_asmiblock
port (
dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
oe : in std_logic;
data0out: out std_logic
);
end component;
end cyclone_components;
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