apex20k_atoms.vhd
来自「一个非常好的dc使用书籍 一个非常好的dc使用书籍」· VHDL 代码 · 共 1,557 行 · 第 1/5 页
VHD
1,557 行
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => (0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- APEX20K_LCELL Model
--
--
LIBRARY IEEE, apex20k;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use apex20k.atom_pack.all;
ENTITY apex20k_asynch_lcell is
GENERIC (operation_mode : string := "normal";
output_mode : string := "comb_and_reg";
lut_mask : string := "ffff";
power_up : string := "low";
cin_used : string := "false";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_cascin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_regin : VitalDelayType01 := DefPropDelay01;
tpd_datab_regin : VitalDelayType01 := DefPropDelay01;
tpd_datac_regin : VitalDelayType01 := DefPropDelay01;
tpd_datad_regin : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin_regin : VitalDelayType01 := DefPropDelay01;
tpd_cascin_regin : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_cascin_cascout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cascout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cascout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cascout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cascout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cascout : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_cascout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_cascin : VitalDelayType01 := DefPropDelay01 );
PORT (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
cascin : in std_logic := '1';
qfbkin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic;
cascout : out std_logic;
regin : out std_logic);
attribute VITAL_LEVEL0 of apex20k_asynch_lcell : ENTITY is TRUE;
end apex20k_asynch_lcell;
ARCHITECTURE vital_le of apex20k_asynch_lcell is
attribute VITAL_LEVEL0 of vital_le : ARCHITECTURE is TRUE;
signal dataa_ipd, datab_ipd : std_logic;
signal datac_ipd, datad_ipd, cin_ipd, cascin_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (cascin_ipd, cascin, tipd_cascin);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd, cin_ipd, cascin_ipd, qfbkin)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable cascout_VitalGlitchData : VitalGlitchDataType;
variable regin_VitalGlitchData : VitalGlitchDataType;
variable icomb, icomb1, icout : std_logic;
variable idata, setbit : std_logic := '0';
variable tmp_combout, tmp_cascout, tmp_cout, tmp_regin : std_logic;
variable lut_mask_std : std_logic_vector (15 downto 0) := str_to_bin(lut_mask); -- Added By ModelTech
begin
if operation_mode = "normal" then
if cin_used = "true" then
icomb1 := VitalMUX(data => lut_mask_std,
dselect => (datad_ipd, cin_ipd, datab_ipd, dataa_ipd)); -- Added By ModelTech
else
icomb1 := VitalMUX(data => lut_mask_std,
dselect => (datad_ipd, datac_ipd, datab_ipd, dataa_ipd)); -- Added By ModelTech
end if;
icomb := icomb1 and cascin_ipd;
end if;
if operation_mode = "arithmetic" then
icomb1 := VitalMUX(data => lut_mask_std,
dselect => ('1', cin_ipd, datab_ipd, dataa_ipd)); -- Added By ModelTech
icout := VitalMUX(data => lut_mask_std,
dselect => ('0', cin_ipd, datab_ipd, dataa_ipd)); -- Added By ModelTech
icomb := icomb1 and cascin_ipd;
end if;
if operation_mode = "counter" then
icomb1 := VitalMUX(data => lut_mask_std,
dselect => ('1', cin_ipd, datab_ipd, dataa_ipd)); -- Added By ModelTech
icout := VitalMUX(data => lut_mask_std,
dselect => ('0', cin_ipd, datab_ipd, dataa_ipd)); -- Added By ModelTech
icomb := icomb1 and cascin_ipd;
end if;
if operation_mode = "qfbk_counter" then
icomb1 := VitalMUX(data => lut_mask_std,
dselect => ('1', qfbkin, datab_ipd, dataa_ipd)); -- Added By ModelTech
icout := VitalMUX(data => lut_mask_std,
dselect => ('0', qfbkin, datab_ipd, dataa_ipd)); -- Added By ModelTech
icomb := icomb1 and cascin_ipd;
end if;
tmp_combout := icomb;
tmp_cascout := icomb;
tmp_cout := icout;
tmp_regin := icomb;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => tmp_combout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE),
5 => (cascin_ipd'last_event, tpd_cascin_combout, TRUE),
6 => (qfbkin'last_event, tpd_qfbkin_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => regin,
OutSignalName => "REGIN",
OutTemp => tmp_regin,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_regin, TRUE),
1 => (datab_ipd'last_event, tpd_datab_regin, TRUE),
2 => (datac_ipd'last_event, tpd_datac_regin, TRUE),
3 => (datad_ipd'last_event, tpd_datad_regin, TRUE),
4 => (cin_ipd'last_event, tpd_cin_regin, TRUE),
5 => (cascin_ipd'last_event, tpd_cascin_regin, TRUE),
6 => (qfbkin'last_event, tpd_qfbkin_regin, TRUE)),
GlitchData => regin_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cascout,
OutSignalName => "CASCOUT",
OutTemp => tmp_cascout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cascout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cascout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cascout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cascout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_cascout, TRUE),
5 => (cascin_ipd'last_event, tpd_cascin_cascout, TRUE),
6 => (qfbkin'last_event, tpd_qfbkin_cascout, TRUE)),
GlitchData => cascout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => tmp_cout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
5 => (qfbkin'last_event, tpd_qfbkin_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_le;
LIBRARY IEEE, apex20k;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use apex20k.atom_pack.all;
ENTITY apex20k_lcell_register is
GENERIC (
power_up : string := "low";
packed_mode : string := "false";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_qfbko_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_qfbko_posedge : VitalDelayType01 := DefPropDelay01;
tperiod_clk_posedge : VitalDelayType := DefPulseWdthCnst;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01);
PORT (clk :in std_logic;
datain : in std_logic := '1';
datac : in std_logic := '1';
aclr : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic;
qfbko : out std_logic);
attribute VITAL_LEVEL0 of apex20k_lcell_register : ENTITY is TRUE;
end apex20k_lcell_register;
ARCHITECTURE vital_le_reg of apex20k_lcell_register is
attribute VITAL_LEVEL0 of vital_le_reg : ARCHITECTURE is TRUE;
signal ena_ipd, sload_ipd, datac_ipd : std_logic;
signal clk_ipd, aclr_ipd, sclr_ipd : std_logic;
begin
---------------------
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