apex20ke_components_87.vhd
来自「一个非常好的dc使用书籍 一个非常好的dc使用书籍」· VHDL 代码 · 共 813 行 · 第 1/4 页
VHD
813 行
tsetup_slavehreadyi_slavehclk : VitalDelayType := DefSetupHoldCnst;
tsetup_slavehsel_slavehclk : VitalDelayType := DefSetupHoldCnst;
tsetup_slavehselreg_slavehclk : VitalDelayType := DefSetupHoldCnst;
tsetup_slavehsize_slavehclk : VitalDelayArrayType(1 downto 0) := (others => DefSetupHoldCnst);
tsetup_slavehtrans_slavehclk : VitalDelayArrayType(1 downto 0) := (others => DefSetupHoldCnst);
tsetup_slavehwdata_slavehclk : VitalDelayArrayType(31 downto 0) := (others => DefSetupHoldCnst);
tsetup_slavehwrite_slavehclk : VitalDelayType := DefSetupHoldCnst;
tsetup_debugiebrkpt_masterhclk : VitalDelayType := DefSetupHoldCnst;
tsetup_debugdewpt_masterhclk : VitalDelayType := DefSetupHoldCnst;
tsetup_slavehmastlock_masterhclk : VitalDelayType := DefSetupHoldCnst;
thold_masterhgrant_masterhclk : VitalDelayType := DefSetupHoldCnst;
thold_masterhrdata_masterhclk : VitalDelayArrayType(31 downto 0) := (others => DefSetupHoldCnst);
thold_masterhready_masterhclk : VitalDelayType := DefSetupHoldCnst;
thold_masterhresp_masterhclk : VitalDelayArrayType(1 downto 0) := (others => DefSetupHoldCnst);
thold_slavehaddr_slavehclk : VitalDelayArrayType(31 downto 0) := (others => DefSetupHoldCnst);
thold_slavehburst_slavehclk : VitalDelayArrayType(2 downto 0) := (others => DefSetupHoldCnst);
thold_slavehreadyi_slavehclk : VitalDelayType := DefSetupHoldCnst;
thold_slavehsel_slavehclk : VitalDelayType := DefSetupHoldCnst;
thold_slavehselreg_slavehclk : VitalDelayType := DefSetupHoldCnst;
thold_slavehsize_slavehclk : VitalDelayArrayType(1 downto 0) := (others => DefSetupHoldCnst);
thold_slavehtrans_slavehclk : VitalDelayArrayType(1 downto 0) := (others => DefSetupHoldCnst);
thold_slavehwdata_slavehclk : VitalDelayArrayType(31 downto 0) := (others => DefSetupHoldCnst);
thold_slavehwrite_slavehclk : VitalDelayType := DefSetupHoldCnst;
thold_debugiebrkpt_masterhclk : VitalDelayType := DefSetupHoldCnst;
thold_debugdewpt_masterhclk : VitalDelayType := DefSetupHoldCnst;
thold_slavehmastlock_masterhclk : VitalDelayType := DefSetupHoldCnst );
PORT (
clkref : in std_logic ;
npor : in std_logic ;
nreseti : in std_logic ;
nreseto : out std_logic ;
nresetoe : out std_logic ;
intpld : in std_logic_vector ( 5 downto 0) := (others => '0');
intnmi : in std_logic := '0';
perreset : out std_logic ;
intuart : out std_logic ;
inttimer0 : out std_logic ;
inttimer1 : out std_logic ;
intproc0 : out std_logic ;
intproc1 : out std_logic ;
debugrq : in std_logic := '0';
debugext0 : in std_logic := '0';
debugext1 : in std_logic := '0';
debugiebrkpt : in std_logic := '0';
debugdewpt : in std_logic := '0';
debugextin : in std_logic_vector ( 3 downto 0) := (others => '0');
debugack : out std_logic ;
debugrng0 : out std_logic ;
debugrng1 : out std_logic ;
debugextout : out std_logic_vector ( 3 downto 0) ;
slavehclk : in std_logic := '0';
slavehwrite : in std_logic := '0';
slavehreadyi : in std_logic := '0';
slavehselreg : in std_logic := '0';
slavehsel : in std_logic := '0';
slavehmastlock : in std_logic := '0';
slavehaddr : in std_logic_vector (31 downto 0) := (others => '0');
slavehwdata : in std_logic_vector (31 downto 0) := (others => '0');
slavehtrans : in std_logic_vector ( 1 downto 0) := (others => '0');
slavehsize : in std_logic_vector ( 1 downto 0) := (others => '0');
slavehburst : in std_logic_vector ( 2 downto 0) := (others => '0');
slavehreadyo : out std_logic ;
slavebuserrint : out std_logic ;
slavehrdata : out std_logic_vector (31 downto 0) ;
slavehresp : out std_logic_vector ( 1 downto 0) ;
masterhclk : in std_logic := '0';
masterhrdata : in std_logic_vector (31 downto 0) := (others => '0');
masterhresp : in std_logic_vector ( 1 downto 0) := (others => '0');
masterhwrite : out std_logic ;
masterhlock : out std_logic ;
masterhbusreq : out std_logic ;
masterhaddr : out std_logic_vector (31 downto 0) ;
masterhwdata : out std_logic_vector (31 downto 0) ;
masterhtrans : out std_logic_vector ( 1 downto 0) ;
masterhsize : out std_logic_vector ( 1 downto 0) ;
masterhready : in std_logic := '0';
masterhburst : out std_logic_vector ( 2 downto 0) ;
masterhgrant : in std_logic := '0';
lockreqdp0 : in std_logic := '0';
lockreqdp1 : in std_logic := '0';
lockgrantdp0 : out std_logic ;
lockgrantdp1 : out std_logic ;
ebiack : in std_logic := '0';
ebiwen : out std_logic ;
ebioen : out std_logic ;
ebiclk : out std_logic ;
ebibe : out std_logic_vector ( 1 downto 0) ;
ebicsn : out std_logic_vector ( 3 downto 0) ;
ebiaddr : out std_logic_vector (24 downto 0) ;
ebidqoe : out std_logic ;
ebidqout : out std_logic_vector (15 downto 0) ;
ebidqin : in std_logic_vector (15 downto 0) := (others => '0');
uarttxd : out std_logic ;
uartrtsn : out std_logic ;
uartdtrn : out std_logic ;
uartctsn : in std_logic := '0';
uartdsrn : in std_logic := '0';
uartrxd : in std_logic := '0';
uartdcdon : out std_logic ;
uartdcdin : in std_logic := '0';
uartriin : in std_logic := '0';
uartrion : out std_logic ;
uartdcdrioe : out std_logic ;
sdramclk : out std_logic ;
sdramclkn : out std_logic ;
sdramclke : out std_logic ;
sdramwen : out std_logic ;
sdramcasn : out std_logic ;
sdramrasn : out std_logic ;
sdramdqm : out std_logic_vector (sdramdqm_width-1 downto 0) ;
sdramaddr : out std_logic_vector (14 downto 0) ;
sdramdqoe : out std_logic_vector (sdramdqm_width-1 downto 0) ;
sdramdqout : out std_logic_vector (sdram_width-1 downto 0) ;
sdramdqin : in std_logic_vector (sdram_width-1 downto 0) := (others => '0');
sdramdqsoe : out std_logic ;
sdramcsn : out std_logic_vector ( 1 downto 0) ;
sdramdqsout : out std_logic_vector (sdramdqm_width-1 downto 0) ;
sdramdqsin : in std_logic_vector (sdramdqm_width-1 downto 0) := (others => '0');
intextpin : in std_logic := '0';
traceclk : out std_logic ;
tracesync : out std_logic ;
tracepipestat : out std_logic_vector ( 2 downto 0) ;
tracepkt : out std_logic_vector (15 downto 0) ;
gpi : in std_logic_vector (gpio_width-1 downto 0) := (others =>'0');
gpo : out std_logic_vector (gpio_width-1 downto 0) );
END COMPONENT;
COMPONENT apex20ke_jtagb
PORT (tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic);
END COMPONENT;
COMPONENT apex20ke_stripe
GENERIC (
dp0crambits : std_logic_vector(3 downto 0) := "0000";
dp1crambits : std_logic_vector(3 downto 0) := "0000";
globaldpcrambits : std_logic_vector(1 downto 0) := "00";
device_size : integer := 1000;
spare_width : integer := 5;
dpram_a0width : integer := 16;
processor : string := "ARM";
boot_from_flash : string := "true";
debug_extensions : string := "false";
ebi0_width : integer := 16;
use_short_reset : string := "true";
use_initialisation_files : string := "true";
tipd_clkref : VitalDelayType01 := DefPropDelay01;
tipd_slavhclk : VitalDelayType01 := DefPropDelay01;
tipd_shwrite : VitalDelayType01 := DefPropDelay01;
tipd_shreadyi : VitalDelayType01 := DefPropDelay01;
tipd_shselreg : VitalDelayType01 := DefPropDelay01;
tipd_shsel : VitalDelayType01 := DefPropDelay01;
tipd_shmastlock : VitalDelayType01 := DefPropDelay01;
tipd_shaddr : VitalDelayArrayType01(31 downto 0) := (others => DefPropDelay01);
tipd_shwdata : VitalDelayArrayType01(31 downto 0) := (others => DefPropDelay01);
tipd_shtrans : VitalDelayArrayType01(1 downto 0) := (others => DefPropDelay01);
tipd_shsize : VitalDelayArrayType01(1 downto 0) := (others => DefPropDelay01);
tipd_shburst : VitalDelayArrayType01(2 downto 0) := (others => DefPropDelay01);
tipd_masthclk : VitalDelayType01 := DefPropDelay01;
tipd_mhready : VitalDelayType01 := DefPropDelay01;
tipd_mhgrant : VitalDelayType01 := DefPropDelay01;
tipd_mhrdata : VitalDelayArrayType01(31 downto 0) := (others => DefPropDelay01);
tipd_mhresp : VitalDelayArrayType01(1 downto 0) := (others => DefPropDelay01);
tipd_debugbusout : VitalDelayArrayType01(8 downto 0) := (others => DefPropDelay01);
tipd_intbusout : VitalDelayArrayType01(5 downto 0) := (others => DefPropDelay01);
tipd_intextpin : VitalDelayType01 := DefPropDelay01;
tipd_ebiack : VitalDelayType01 := DefPropDelay01;
tipd_ebidqin : VitalDelayArrayType01(15 downto 0) := (others => DefPropDelay01);
tipd_uartctsn : VitalDelayType01 := DefPropDelay01;
tipd_uartdsrn : VitalDelayType01 := DefPropDelay01;
tipd_uartrxd : VitalDelayType01 := DefPropDelay01;
tipd_uartdcdin : VitalDelayType01 := DefPropDelay01;
tipd_uartriin : VitalDelayType01 := DefPropDelay01;
tipd_sdramdqin : VitalDelayArrayType01(31 downto 0) := (others => DefPropDelay01);
tipd_sdramdqsin : VitalDelayArrayType01(3 downto 0) := (others => DefPropDelay01);
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