apex20ke_components_87.vhd
来自「一个非常好的dc使用书籍 一个非常好的dc使用书籍」· VHDL 代码 · 共 813 行 · 第 1/4 页
VHD
813 行
tsetup_datain_clk1_noedge_negedge : VitalDelayArrayType(7 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_clk1_noedge_negedge : VitalDelayArrayType(7 downto 0) := (OTHERS => DefSetupHoldCnst);
tpd_clk0_dataout_negedge: VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_clk1 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(7 downto 0) := (
OTHERS => DefpropDelay01));
PORT (
clk0 : in std_logic;
clk1 : in std_logic;
datain : in std_logic_vector(7 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic);
END COMPONENT;
COMPONENT apex20ke_lvds_receiver
GENERIC (
channel_width : integer := 8;
-- power_up : string := "low";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_negedge: VitalDelayArrayType01(7 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_clk1 : VitalDelayType01 := DefpropDelay01;
tipd_deskewin : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01);
PORT (
clk0 : in std_logic;
clk1 : in std_logic;
datain : in std_logic;
deskewin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(7 downto 0));
END COMPONENT;
COMPONENT apex20ke_pll
GENERIC (input_frequency : integer := 1000;
operation_mode : string := "normal";
simulation_type : string := "timing";
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
phase_shift : integer := 0;
effective_phase_shift : integer := 0;
effective_clk0_delay : integer := 0;
effective_clk1_delay : integer := 0;
lock_high : integer := 1;
invalid_lock_multiplier : integer := 5;
valid_lock_multiplier : integer := 5;
lock_low : integer := 1;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_ena_clk0 : VitalDelayType01 := DefPropDelay01;
tpd_ena_clk1 : VitalDelayType01 := DefPropDelay01;
tpd_clk_locked : VitalDelayType01 := DefPropDelay01;
tpd_fbin_clk0 : VitalDelayType01 := DefPropDelay01;
tpd_fbin_clk1 : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_fbin : VitalDelayType01 := DefpropDelay01
);
PORT (clk : in std_logic;
ena : in std_logic := '1';
fbin : in std_logic := '0';
clk0 : out std_logic;
clk1 : out std_logic;
locked : out std_logic
);
END COMPONENT;
COMPONENT apex20ke_dpram
GENERIC (
operation_mode : string;
output_mode : string;
width : integer;
addrwidth : integer;
depth : integer;
ramblock : integer := -1;
ramcontent : string := "none" ;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_portadatain : VitalDelayArrayType01(63 downto 0) := (OTHERS => DefPropDelay01);
tipd_portbdatain : VitalDelayArrayType01(15 downto 0) := (OTHERS => DefPropDelay01);
tipd_portaaddr : VitalDelayArrayType01(16 downto 0) := (OTHERS => DefPropDelay01);
tipd_portbaddr : VitalDelayArrayType01(14 downto 0) := (OTHERS => DefPropDelay01);
tipd_portaclk : VitalDelayType01 := DefPropDelay01;
tipd_portbclk : VitalDelayType01 := DefPropDelay01;
tipd_portawe : VitalDelayType01 := DefPropDelay01;
tipd_portbwe : VitalDelayType01 := DefPropDelay01;
tipd_portaena : VitalDelayType01 := DefPropDelay01;
tipd_portbena : VitalDelayType01 := DefPropDelay01;
tpd_portaclk_portadataout_posedge : VitalDelayArrayType01(63 downto 0) := (OTHERS => DefPropDelay01);
tpd_portbclk_portbdataout_posedge : VitalDelayArrayType01(15 downto 0) := (OTHERS => DefPropDelay01);
tsetup_portadataout_portaclk_noedge_posedge : VitalDelayArrayType (63 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_portbdataout_portbclk_noedge_posedge : VitalDelayArrayType (15 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_portadataout_portaclk_noedge_posedge : VitalDelayArrayType (63 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_portbdataout_portbclk_noedge_posedge : VitalDelayArrayType (15 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_portadatain_portaclk_noedge_posedge : VitalDelayArrayType (63 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_portbdatain_portbclk_noedge_posedge : VitalDelayArrayType (15 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_portadatain_portaclk_noedge_posedge : VitalDelayArrayType (63 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_portbdatain_portbclk_noedge_posedge : VitalDelayArrayType (15 downto 0) := (OTHERS => DefSetupHoldCnst));
PORT (
portaclk : in std_logic := '0';
portaena : in std_logic := '0';
portawe : in std_logic := '0';
portaaddr : in std_logic_vector(addrwidth-1 downto 0) := (others => '0');
portadatain : in std_logic_vector(width-1 downto 0) := (others => '0');
portadataout : out std_logic_vector(width-1 downto 0) ;
portbclk : in std_logic := '0';
portbena : in std_logic := '0';
portbwe : in std_logic := '0';
portbaddr : in std_logic_vector(addrwidth-1 downto 0) := (others => '0');
portbdatain : in std_logic_vector(width-1 downto 0) := (others => '0');
portbdataout : out std_logic_vector(width-1 downto 0));
END COMPONENT;
COMPONENT apex20ke_upcore
GENERIC (
processor : string := "arm" ;
source : string := "" ;
sdram_width : integer := 32 ;
sdramdqm_width : integer := 4 ;
gpio_width : integer := 4 ;
MsgOn : Boolean := DefGlitchMsgOn ;
XOn : Boolean := DefGlitchXOn ;
MsgOnChecks : Boolean := DefMsgOnChecks ;
XOnChecks : Boolean := DefXOnChecks ;
InstancePath : String := "*" ;
tipd_clkref : VitalDelayType01 := DefPropDelay01;
tipd_npor : VitalDelayType01 := DefPropDelay01;
tipd_nreseti : VitalDelayType01 := DefPropDelay01;
tipd_intpld : VitalDelayArrayType01 ( 5 downto 0) := (others => DefPropDelay01);
tipd_intnmi : VitalDelayType01 := DefPropDelay01;
tipd_debugrq : VitalDelayType01 := DefPropDelay01;
tipd_debugext0 : VitalDelayType01 := DefPropDelay01;
tipd_debugext1 : VitalDelayType01 := DefPropDelay01;
tipd_debugiebrkpt : VitalDelayType01 := DefPropDelay01;
tipd_debugdewpt : VitalDelayType01 := DefPropDelay01;
tipd_debugextin : VitalDelayArrayType01 ( 3 downto 0) := (others => DefPropDelay01);
tipd_slavehclk : VitalDelayType01 := DefPropDelay01;
tipd_slavehwrite : VitalDelayType01 := DefPropDelay01;
tipd_slavehreadyi : VitalDelayType01 := DefPropDelay01;
tipd_slavehselreg : VitalDelayType01 := DefPropDelay01;
tipd_slavehsel : VitalDelayType01 := DefPropDelay01;
tipd_slavehmastlock : VitalDelayType01 := DefPropDelay01;
tipd_slavehaddr : VitalDelayArrayType01 (31 downto 0) := (others => DefPropDelay01);
tipd_slavehwdata : VitalDelayArrayType01 (31 downto 0) := (others => DefPropDelay01);
tipd_slavehtrans : VitalDelayArrayType01 ( 1 downto 0) := (others => DefPropDelay01);
tipd_slavehsize : VitalDelayArrayType01 ( 1 downto 0) := (others => DefPropDelay01);
tipd_slavehburst : VitalDelayArrayType01 ( 2 downto 0) := (others => DefPropDelay01);
tipd_masterhclk : VitalDelayType01 := DefPropDelay01;
tipd_masterhrdata : VitalDelayArrayType01 (31 downto 0) := (others => DefPropDelay01);
tipd_masterhresp : VitalDelayArrayType01 ( 1 downto 0) := (others => DefPropDelay01);
tipd_masterhready : VitalDelayType01 := DefPropDelay01;
tipd_masterhgrant : VitalDelayType01 := DefPropDelay01;
tipd_lockreqdp0 : VitalDelayType01 := DefPropDelay01;
tipd_lockreqdp1 : VitalDelayType01 := DefPropDelay01;
tipd_ebiack : VitalDelayType01 := DefPropDelay01;
tipd_ebidqin : VitalDelayArrayType01 (15 downto 0) := (others => DefPropDelay01);
tipd_uartctsn : VitalDelayType01 := DefPropDelay01;
tipd_uartdsrn : VitalDelayType01 := DefPropDelay01;
tipd_uartrxd : VitalDelayType01 := DefPropDelay01;
tipd_uartdcdin : VitalDelayType01 := DefPropDelay01;
tipd_uartriin : VitalDelayType01 := DefPropDelay01;
tipd_sdramdqin : VitalDelayArrayType01 (31 downto 0) := (others => DefPropDelay01);
tipd_sdramdqsin : VitalDelayArrayType01 ( 3 downto 0) := (others => DefPropDelay01);
tipd_intextpin : VitalDelayType01 := DefPropDelay01;
tipd_gpi : VitalDelayArrayType01 ( 5 downto 0) := (others => DefPropDelay01);
tpd_slavehclk_slavehreadyo_posedge : VitalDelayType01 := DefPropDelay01;
tpd_slavehclk_slavebuserrint_posedge : VitalDelayType01 := DefPropDelay01;
tpd_slavehclk_slavehrdata_posedge : VitalDelayArrayType01(31 downto 0) := (others => DefPropDelay01);
tpd_slavehclk_slavehresp_posedge : VitalDelayArrayType01(1 downto 0) := (others => DefPropDelay01);
tpd_masterhclk_masterhlock_posedge : VitalDelayType01 := DefPropDelay01;
tpd_masterhclk_masterhwrite_posedge : VitalDelayType01 := DefPropDelay01;
tpd_masterhclk_masterhbusreq_posedge : VitalDelayType01 := DefPropDelay01;
tpd_masterhclk_masterhaddr_posedge : VitalDelayArrayType01(31 downto 0) := (others => DefPropDelay01);
tpd_masterhclk_masterhwdata_posedge : VitalDelayArrayType01(31 downto 0) := (others => DefPropDelay01);
tpd_masterhclk_masterhtrans_posedge : VitalDelayArrayType01(1 downto 0) := (others => DefPropDelay01);
tpd_masterhclk_masterhsize_posedge : VitalDelayArrayType01(1 downto 0) := (others => DefPropDelay01);
tpd_masterhclk_masterhburst_posedge : VitalDelayArrayType01(2 downto 0) := (others => DefPropDelay01);
tsetup_masterhgrant_masterhclk : VitalDelayType := DefSetupHoldCnst;
tsetup_masterhrdata_masterhclk : VitalDelayArrayType(31 downto 0) := (others => DefSetupHoldCnst);
tsetup_masterhready_masterhclk : VitalDelayType := DefSetupHoldCnst;
tsetup_masterhresp_masterhclk : VitalDelayArrayType(1 downto 0) := (others => DefSetupHoldCnst);
tsetup_slavehaddr_slavehclk : VitalDelayArrayType(31 downto 0) := (others => DefSetupHoldCnst);
tsetup_slavehburst_slavehclk : VitalDelayArrayType(2 downto 0) := (others => DefSetupHoldCnst);
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