max_atoms.vhd
来自「一个非常好的dc使用书籍 一个非常好的dc使用书籍」· VHDL 代码 · 共 1,251 行 · 第 1/5 页
VHD
1,251 行
VitalWireDelay (pterm5_ipd(8), pterm5(8), tipd_pterm5(8));
VitalWireDelay (pterm5_ipd(9), pterm5(9), tipd_pterm5(9));
VitalWireDelay (pterm5_ipd(10), pterm5(10), tipd_pterm5(10));
VitalWireDelay (pterm5_ipd(11), pterm5(11), tipd_pterm5(11));
VitalWireDelay (pterm5_ipd(12), pterm5(12), tipd_pterm5(12));
VitalWireDelay (pterm5_ipd(13), pterm5(13), tipd_pterm5(13));
VitalWireDelay (pterm5_ipd(14), pterm5(14), tipd_pterm5(14));
VitalWireDelay (pterm5_ipd(15), pterm5(15), tipd_pterm5(15));
VitalWireDelay (pterm5_ipd(16), pterm5(16), tipd_pterm5(16));
VitalWireDelay (pterm5_ipd(17), pterm5(17), tipd_pterm5(17));
VitalWireDelay (pterm5_ipd(18), pterm5(18), tipd_pterm5(18));
VitalWireDelay (pterm5_ipd(19), pterm5(19), tipd_pterm5(19));
VitalWireDelay (pterm5_ipd(20), pterm5(20), tipd_pterm5(20));
VitalWireDelay (pterm5_ipd(21), pterm5(21), tipd_pterm5(21));
VitalWireDelay (pterm5_ipd(22), pterm5(22), tipd_pterm5(22));
VitalWireDelay (pterm5_ipd(23), pterm5(23), tipd_pterm5(23));
VitalWireDelay (pterm5_ipd(24), pterm5(24), tipd_pterm5(24));
VitalWireDelay (pterm5_ipd(25), pterm5(25), tipd_pterm5(25));
VitalWireDelay (pterm5_ipd(26), pterm5(26), tipd_pterm5(26));
VitalWireDelay (pterm5_ipd(27), pterm5(27), tipd_pterm5(27));
VitalWireDelay (pterm5_ipd(28), pterm5(28), tipd_pterm5(28));
VitalWireDelay (pterm5_ipd(29), pterm5(29), tipd_pterm5(29));
VitalWireDelay (pterm5_ipd(30), pterm5(30), tipd_pterm5(30));
VitalWireDelay (pterm5_ipd(31), pterm5(31), tipd_pterm5(31));
VitalWireDelay (pterm5_ipd(32), pterm5(32), tipd_pterm5(32));
VitalWireDelay (pterm5_ipd(33), pterm5(33), tipd_pterm5(33));
VitalWireDelay (pterm5_ipd(34), pterm5(34), tipd_pterm5(34));
VitalWireDelay (pterm5_ipd(35), pterm5(35), tipd_pterm5(35));
VitalWireDelay (pterm5_ipd(36), pterm5(36), tipd_pterm5(36));
VitalWireDelay (pterm5_ipd(37), pterm5(37), tipd_pterm5(37));
VitalWireDelay (pterm5_ipd(38), pterm5(38), tipd_pterm5(38));
VitalWireDelay (pterm5_ipd(39), pterm5(39), tipd_pterm5(39));
VitalWireDelay (pterm5_ipd(40), pterm5(40), tipd_pterm5(40));
VitalWireDelay (pterm5_ipd(41), pterm5(41), tipd_pterm5(41));
VitalWireDelay (pterm5_ipd(42), pterm5(42), tipd_pterm5(42));
VitalWireDelay (pterm5_ipd(43), pterm5(43), tipd_pterm5(43));
VitalWireDelay (pterm5_ipd(44), pterm5(44), tipd_pterm5(44));
VitalWireDelay (pterm5_ipd(45), pterm5(45), tipd_pterm5(45));
VitalWireDelay (pterm5_ipd(46), pterm5(46), tipd_pterm5(46));
VitalWireDelay (pterm5_ipd(47), pterm5(47), tipd_pterm5(47));
VitalWireDelay (pterm5_ipd(48), pterm5(48), tipd_pterm5(48));
VitalWireDelay (pterm5_ipd(49), pterm5(49), tipd_pterm5(49));
VitalWireDelay (pterm5_ipd(50), pterm5(50), tipd_pterm5(50));
VitalWireDelay (pterm5_ipd(51), pterm5(51), tipd_pterm5(51));
VitalWireDelay (pxor_ipd(0), pxor(0), tipd_pxor(0));
VitalWireDelay (pxor_ipd(1), pxor(1), tipd_pxor(1));
VitalWireDelay (pxor_ipd(2), pxor(2), tipd_pxor(2));
VitalWireDelay (pxor_ipd(3), pxor(3), tipd_pxor(3));
VitalWireDelay (pxor_ipd(4), pxor(4), tipd_pxor(4));
VitalWireDelay (pxor_ipd(5), pxor(5), tipd_pxor(5));
VitalWireDelay (pxor_ipd(6), pxor(6), tipd_pxor(6));
VitalWireDelay (pxor_ipd(7), pxor(7), tipd_pxor(7));
VitalWireDelay (pxor_ipd(8), pxor(8), tipd_pxor(8));
VitalWireDelay (pxor_ipd(9), pxor(9), tipd_pxor(9));
VitalWireDelay (pxor_ipd(10), pxor(10), tipd_pxor(10));
VitalWireDelay (pxor_ipd(11), pxor(11), tipd_pxor(11));
VitalWireDelay (pxor_ipd(12), pxor(12), tipd_pxor(12));
VitalWireDelay (pxor_ipd(13), pxor(13), tipd_pxor(13));
VitalWireDelay (pxor_ipd(14), pxor(14), tipd_pxor(14));
VitalWireDelay (pxor_ipd(15), pxor(15), tipd_pxor(15));
VitalWireDelay (pxor_ipd(16), pxor(16), tipd_pxor(16));
VitalWireDelay (pxor_ipd(17), pxor(17), tipd_pxor(17));
VitalWireDelay (pxor_ipd(18), pxor(18), tipd_pxor(18));
VitalWireDelay (pxor_ipd(19), pxor(19), tipd_pxor(19));
VitalWireDelay (pxor_ipd(20), pxor(20), tipd_pxor(20));
VitalWireDelay (pxor_ipd(21), pxor(21), tipd_pxor(21));
VitalWireDelay (pxor_ipd(22), pxor(22), tipd_pxor(22));
VitalWireDelay (pxor_ipd(23), pxor(23), tipd_pxor(23));
VitalWireDelay (pxor_ipd(24), pxor(24), tipd_pxor(24));
VitalWireDelay (pxor_ipd(25), pxor(25), tipd_pxor(25));
VitalWireDelay (pxor_ipd(26), pxor(26), tipd_pxor(26));
VitalWireDelay (pxor_ipd(27), pxor(27), tipd_pxor(27));
VitalWireDelay (pxor_ipd(28), pxor(28), tipd_pxor(28));
VitalWireDelay (pxor_ipd(29), pxor(29), tipd_pxor(29));
VitalWireDelay (pxor_ipd(30), pxor(30), tipd_pxor(30));
VitalWireDelay (pxor_ipd(31), pxor(31), tipd_pxor(31));
VitalWireDelay (pxor_ipd(32), pxor(32), tipd_pxor(32));
VitalWireDelay (pxor_ipd(33), pxor(33), tipd_pxor(33));
VitalWireDelay (pxor_ipd(34), pxor(34), tipd_pxor(34));
VitalWireDelay (pxor_ipd(35), pxor(35), tipd_pxor(35));
VitalWireDelay (pxor_ipd(36), pxor(36), tipd_pxor(36));
VitalWireDelay (pxor_ipd(37), pxor(37), tipd_pxor(37));
VitalWireDelay (pxor_ipd(38), pxor(38), tipd_pxor(38));
VitalWireDelay (pxor_ipd(39), pxor(39), tipd_pxor(39));
VitalWireDelay (pxor_ipd(40), pxor(40), tipd_pxor(40));
VitalWireDelay (pxor_ipd(41), pxor(41), tipd_pxor(41));
VitalWireDelay (pxor_ipd(42), pxor(42), tipd_pxor(42));
VitalWireDelay (pxor_ipd(43), pxor(43), tipd_pxor(43));
VitalWireDelay (pxor_ipd(44), pxor(44), tipd_pxor(44));
VitalWireDelay (pxor_ipd(45), pxor(45), tipd_pxor(45));
VitalWireDelay (pxor_ipd(46), pxor(46), tipd_pxor(46));
VitalWireDelay (pxor_ipd(47), pxor(47), tipd_pxor(47));
VitalWireDelay (pxor_ipd(48), pxor(48), tipd_pxor(48));
VitalWireDelay (pxor_ipd(49), pxor(49), tipd_pxor(49));
VitalWireDelay (pxor_ipd(50), pxor(50), tipd_pxor(50));
VitalWireDelay (pxor_ipd(51), pxor(51), tipd_pxor(51));
VitalWireDelay (pexpin_ipd, pexpin, tipd_pexpin);
VitalWireDelay (fpin_ipd, fpin, tipd_fpin);
end block;
VITALtiming : process(pterm0_ipd, pterm1_ipd, pterm2_ipd, pterm3_ipd, pterm4_ipd, pterm5_ipd, pxor_ipd, pexpin_ipd, fbkin, fpin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable regin_VitalGlitchData : VitalGlitchDataType;
variable pexpout_VitalGlitchData : VitalGlitchDataType;
variable tmp_comb, tmp_pexpout : std_logic;
begin
if (pexp_mode = "off") then
if (operation_mode = "normal") then
if (register_mode = "tff") then
tmp_comb := ((product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd) xor fbkin;
else
tmp_comb := (product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd;
end if;
elsif (operation_mode = "invert") then
if (register_mode = "tff") then
tmp_comb := (((product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd)) xor (not(fbkin));
else
tmp_comb := ((product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd) xor '1';
end if;
elsif (operation_mode = "xor") then
tmp_comb := ((product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd) xor product(pxor_ipd);
elsif (operation_mode = "vcc") then
if (register_mode = "tff") then
tmp_comb := '1' xor fbkin;
else
tmp_comb := fpin_ipd;
end if;
else
tmp_comb := 'Z';
tmp_pexpout := 'Z';
end if;
elsif (pexp_mode = "on") then
if (operation_mode = "normal") then
if (register_mode = "tff") then
tmp_comb := (product (pterm5_ipd)) xor fbkin;
else
tmp_comb := product (pterm5_ipd);
end if;
tmp_pexpout := (product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd;
elsif (operation_mode = "invert") then
if (register_mode = "tff") then
tmp_comb := (product(pterm5_ipd)) xor (not(fbkin));
else
tmp_comb := (product(pterm5_ipd)) xor '1';
end if;
tmp_pexpout := (product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd;
elsif (operation_mode = "xor") then
tmp_pexpout := (product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd;
tmp_comb := (product(pterm5_ipd)) xor (product(pxor_ipd));
elsif (operation_mode = "vcc") then
if (register_mode = "tff") then
tmp_comb := '1' xor fbkin;
else
tmp_comb := fpin_ipd;
end if;
tmp_pexpout := (product(pterm0) or product(pterm1) or product(pterm2) or product(pterm3) or product(pterm4)) or pexpin_ipd;
else
tmp_comb := 'Z';
tmp_pexpout := 'Z';
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => tmp_comb,
Paths => (1 => (pterm0_ipd'last_event, tpd_pterm0_combout(0), TRUE),
2 => (pterm1_ipd'last_event, tpd_pterm1_combout(0), TRUE),
3 => (pterm2_ipd'last_event, tpd_pterm2_combout(0), TRUE),
4 => (pterm3_ipd'last_event, tpd_pterm3_combout(0), TRUE),
5 => (pterm4_ipd'last_event, tpd_pterm4_combout(0), TRUE),
6 => (pterm5_ipd'last_event, tpd_pterm5_combout(0), TRUE),
7 => (pxor_ipd'last_event, tpd_pxor_combout(0), TRUE),
8 => (pexpin_ipd'last_event, tpd_pexpin_combout, TRUE),
9 => (fbkin'last_event, tpd_fbkin_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => pexpout,
OutSignalName => "PEXPOUT",
OutTemp => tmp_pexpout,
Paths => (1 => (pterm0_ipd'last_event, tpd_pterm0_pexpout(0), TRUE),
2 => (pterm1_ipd'last_event, tpd_pterm1_pexpout(0), TRUE),
3 => (pterm2_ipd'last_event, tpd_pterm2_pexpout(0), TRUE),
4 => (pterm3_ipd'last_event, tpd_pterm3_pexpout(0), TRUE),
5 => (pterm4_ipd'last_event, tpd_pterm4_pexpout(0), TRUE),
6 => (pexpin_ipd'last_event, tpd_pexpin_pexpout, TRUE),
7 => (fbkin'last_event, tpd_fbkin_pexpout, TRUE)),
GlitchData => pexpout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => regin,
OutSignalName => "REGIN",
OutTemp => tmp_comb,
Paths => (1 => (pterm0_ipd'last_event, tpd_pterm0_regin(0), TRUE),
2 => (pterm1_ipd'last_event, tpd_pterm1_regin(0), TRUE),
3 => (pterm2_ipd'last_event, tpd_pterm2_regin(0), TRUE),
4 => (pterm3_ipd'last_event, tpd_pterm3_regin(0), TRUE),
5 => (pterm4_ipd'last_event, tpd_pterm4_regin(0), TRUE),
6 => (pterm5_ipd'last_event, tpd_pterm5_regin(0), TRUE),
7 => (fpin_ipd'last_event, tpd_fpin_regin, TRUE),
8 => (pxor_ipd'last_event, tpd_pxor_regin(0), TRUE),
9 => (pexpin_ipd'last_event, tpd_pexpin_regin, TRUE),
10 => (fbkin'last_event, tpd_fbkin_regin, TRUE)),
GlitchData => regin_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_mcell;
library IEEE, max;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use max.atom_pack.all;
entity max_mcell_register is
generic ( operation_mode : string := "normal";
power_up : string := "low";
register_mode : string := "dff";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_pclk_regout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pena_regout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_paclr_regout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_papre_regout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
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